https://gcc.gnu.org/g:fd92765d535a243ecc2941f16cef3386d9c53aff
commit fd92765d535a243ecc2941f16cef3386d9c53aff Author: Pan Li <[email protected]> Date: Sat Sep 6 10:58:29 2025 +0800 RISC-V: Add test for vec_duplicate + vnmsub.vv signed combine with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vnmsub.vv combine to vnmsub.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check for vnmsub.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c: New test. Signed-off-by: Pan Li <[email protected]> (cherry picked from commit 85ff9207c46df5322811aa5baa46fef913da49d3) Diff: --- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c | 1 + .../riscv/rvv/autovec/vx_vf/vx_ternary.h | 2 + .../riscv/rvv/autovec/vx_vf/vx_ternary_data.h | 368 +++++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c | 16 + .../riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c | 16 + .../riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c | 16 + .../riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c | 16 + 18 files changed, 446 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index 29cab3a2e614..8879af34650d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 0e7c9675f5a3..1b7b7401ada7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index 1524e714200d..00d8ef7d85be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index 0967fc3980bd..4480635033aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index fd0098d052f2..d02aaa347dff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index e73ef30ca0f8..5921fe66baef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index ab4c6c22722c..3b5331914692 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index cb9c25305ce1..ca9fa4a30711 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index 881917b95f4f..573ae91bd1fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index e60e2321b3b3..5fab6befc239 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index 3aade3c1f011..5d67e47c4d9b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index 3c7935d75f29..d889a841c4dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h index 06fde11fea8a..987aa7311d04 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h @@ -49,10 +49,12 @@ test_vx_ternary_##NAME##_##T##_case_1 (T * restrict vd, T * restrict vs2, \ DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \ DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, madd) \ DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \ + DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, nmsub) \ #define TEST_TERNARY_VX_UNSIGNED_0(T) \ DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \ DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, madd) \ DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \ + DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, nmsub) \ #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h index 447a58cbace3..08c71fe264ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h @@ -1110,4 +1110,372 @@ uint64_t TEST_TERNARY_DATA(uint64_t, madd)[][4][N] = }, }; +int8_t TEST_TERNARY_DATA(int8_t, nmsub)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 127 }, /* rs1 */ + { /* vs2 */ + 127, 127, 127, 127, + 2, 2, 2, 2, + 0, 0, 0, 0, + -128, -128, -128, -128, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { + 127, 127, 127, 127, + -125, -125, -125, -125, + -8, -8, -8, -8, + 126, 126, 126, 126, + }, + }, +}; + +int16_t TEST_TERNARY_DATA(int16_t, nmsub)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 32767 }, /* rs1 */ + { /* vs2 */ + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { + 32767, 32767, 32767, 32767, + -32765, -32765, -32765, -32765, + -8, -8, -8, -8, + 32766, 32766, 32766, 32766, + }, + }, +}; + +int32_t TEST_TERNARY_DATA(int32_t, nmsub)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 2147483647 }, /* rs1 */ + { /* vs2 */ + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483645, -2147483645, -2147483645, -2147483645, + -8, -8, -8, -8, + 2147483646, 2147483646, 2147483646, 2147483646, + }, + }, +}; + +int64_t TEST_TERNARY_DATA(int64_t, nmsub)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 9223372036854775807ull }, /* rs1 */ + { /* vs2 */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, + -8, -8, -8, -8, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + }, + }, +}; + +uint8_t TEST_TERNARY_DATA(uint8_t, nmsub)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 128 }, /* rs1 */ + { /* vs2 */ + 127, 127, 127, 127, + 255, 255, 255, 255, + 254, 254, 254, 254, + 252, 252, 252, 252, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 254, 254, 254, 254, + 252, 252, 252, 252, + }, + }, +}; + +uint16_t TEST_TERNARY_DATA(uint16_t, nmsub)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 32768 }, /* rs1 */ + { /* vs2 */ + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 65532, 65532, 65532, 65532, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 65534, 65534, 65534, 65534, + 65532, 65532, 65532, 65532, + }, + }, +}; + +uint32_t TEST_TERNARY_DATA(uint32_t, nmsub)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 2147483648 }, /* rs1 */ + { /* vs2 */ + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + }, +}; + +uint64_t TEST_TERNARY_DATA(uint64_t, nmsub)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 9223372036854775808ull }, /* rs1 */ + { /* vs2 */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c new file mode 100644 index 000000000000..5d0c33abf00b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int16_t +#define NAME nmsub +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c new file mode 100644 index 000000000000..e7cd272c3d18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int32_t +#define NAME nmsub +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c new file mode 100644 index 000000000000..c038e5cbff23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int64_t +#define NAME nmsub +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c new file mode 100644 index 000000000000..52325b79d54c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int8_t +#define NAME nmsub +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h"
