https://gcc.gnu.org/g:a3d5eeea62f0353fe0aa8b08a2e7965e47171b17
commit a3d5eeea62f0353fe0aa8b08a2e7965e47171b17 Author: Pan Li <[email protected]> Date: Wed Oct 8 22:15:56 2025 +0800 RISC-V: Add test for vec_duplicate + vwsubu.wv combine with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vwsubu.wv combine to vwsubu.wx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vwsubu.wx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c: New test. Signed-off-by: Pan Li <[email protected]> (cherry picked from commit 17d24e89c4cd7c0af6c6d382e186458248f17002) Diff: --- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 3 +- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 3 +- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h | 1 + .../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 40 ++++++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c | 18 ++++++++++ 12 files changed, 70 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index 76ef2d3f0206..be4d23c2f437 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -13,7 +13,7 @@ TEST_TERNARY_VX_UNSIGNED_0(T) TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vadd.vx} 2 } } */ -/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 2 } } */ /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vand.vx} 1 } } */ /* { dg-final { scan-assembler-times {vor.vx} 1 } } */ @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.wx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index 55fa57dec35d..56dd314a7e16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -13,7 +13,7 @@ TEST_TERNARY_VX_UNSIGNED_0(T) TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vadd.vx} 2 } } */ -/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 2 } } */ /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vand.vx} 1 } } */ /* { dg-final { scan-assembler-times {vor.vx} 1 } } */ @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.wx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index d5176834494e..685f5f631ef5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -36,3 +36,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwaddu.wx} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu.wx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index a234505ce81c..391c59f502a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.wx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index a46c874d0a44..2bcb6a136ff8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.wx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index 94ce774fc2aa..0aa6a212c1e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.wx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index a1278cec61d4..48e095f63ff1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.wx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 910fa6e31580..761ce5d1a56e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.wx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index 9ce0211603ec..1eebec94a6db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.wx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h index 03fba3c2a0c4..5be5f2d456e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h @@ -50,5 +50,6 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_1 (WT * restrict vd, \ DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \ DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, mul) \ DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, +, add) \ + DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, -, sub) \ #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h index faf46a81e6ab..af7d8358ad90 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h @@ -72,6 +72,7 @@ DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul) DEF_BINARY_WIDEN_STRUCT_1(WT, NT, NAME) DEF_BINARY_WIDEN_STRUCT_1_WRAP(uint64_t, uint32_t, add) +DEF_BINARY_WIDEN_STRUCT_1_WRAP(uint64_t, uint32_t, sub) DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = { { @@ -229,4 +230,43 @@ DEF_BINARY_WIDEN_STRUCT_1_DECL_WRAP(uint64_t, uint32_t, add)[] = { }, }; +DEF_BINARY_WIDEN_STRUCT_1_DECL_WRAP(uint64_t, uint32_t, sub)[] = { + { + /* vs2 */ + { + 2147483648, 2147483648, 2147483648, 2147483648, + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull, + }, + /* rs1 */ + 2147483647, + /* expect */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483649, 2147483649, 2147483649, 2147483649, + }, + }, + { + /* vs2 */ + { + 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull, + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 8589934590ull, 8589934590ull, 8589934590ull, 8589934590ull, + 8589934591ull, 8589934591ull, 8589934591ull, 8589934591ull, + }, + /* rs1 */ + 4294967295, + /* expect */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c new file mode 100644 index 000000000000..23043b326efd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c @@ -0,0 +1,18 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_widen.h" +#include "vx_widen_data.h" + +#define WT uint64_t +#define NT uint32_t +#define NAME sub +#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_1_VAR_WRAP(WT, NT, NAME) +#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_1_TYPE_WRAP(WT, NT, NAME) + +DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, -, NAME) + +#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \ + RUN_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, NAME, vd, vs2, rs1, N) + +#include "vx_widen_wx_run.h"
