https://gcc.gnu.org/g:a0ac3ac95f2120138820da7a3fbde1d955f77c3d
commit a0ac3ac95f2120138820da7a3fbde1d955f77c3d Author: Pan Li <[email protected]> Date: Sat Sep 6 11:00:00 2025 +0800 RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned combine with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vnmsub.vvm combine to vnmsub.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vnmsub.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c: New test. Signed-off-by: Pan Li <[email protected]> (cherry picked from commit 409a3c2a35c76479e60ee1ac51766e8625ec6dfd) Diff: --- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 + .../riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c | 16 ++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c | 16 ++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c | 16 ++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c | 16 ++++++++++++++++ 16 files changed, 76 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index b9065ad880ce..d191097e2bb3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index a4d422e2cdd6..e0b4b732c79c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index 7d7ec75c8ea6..65528400b5b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c index 0cdda99b565b..b659f7fbc068 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index f460ccb88650..23479d97b650 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 4ed60f5204cb..8c41bd85686b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index 2a7e3322f9a8..abe16cd7b509 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c index 923b9c34470e..957fcde118fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index 3ddd6b19d681..f232d6a97bd7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 609bdec6eff4..24e187ce2b05 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index a498e53c8e5a..977aa463232e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c index b9b624e1524c..9deb635d0b9c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c new file mode 100644 index 000000000000..95a771d9e726 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint16_t +#define NAME nmsub +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c new file mode 100644 index 000000000000..c013cf9d440e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint32_t +#define NAME nmsub +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c new file mode 100644 index 000000000000..5f62dff5ed8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint64_t +#define NAME nmsub +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c new file mode 100644 index 000000000000..45080898218f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint8_t +#define NAME nmsub +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h"
