https://gcc.gnu.org/g:fea31d2ab6be93cf2db12922ce7fb2b64423b2a2
commit fea31d2ab6be93cf2db12922ce7fb2b64423b2a2 Author: Michael Meissner <[email protected]> Date: Mon Oct 27 19:51:35 2025 -0400 Update comments about making -mbfloat16 and -mfloat16 default. 2025-10-27 Michael Meissner <[email protected]> gcc/ * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Update comments about making -mbfloat16 and -mfloat16 default. (ISA_3_0_MASKS_SERVER): Likewise. (OTHER_POWER10_MASKS): Likewise. (POWERPC_MASKS): Likewise. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 6d7582f93499..9e6a0b801523 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -88,6 +88,15 @@ /* For now, don't provide an embedded version of ISA 2.07. Do not set power8 fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ + +/* In the future consider adding OPTION_MASK_BFLOAT16 and OPTION_MASK_FLOAT16 + when the 16-bit floating support is less experimental. ISA 2.7 (power8) is + the minimum ISA that can support 16-bit point floating point because we need + direct move to load 16-bit values into floating point/vector registers from + GPRs. ISA 3.0 (power9) adds the ability to load/store 16-bit values + directly to floating point/vector registers, and hardware instructions to + convert between _Float16 and float. ISA 3.1 (power10) adds instructions to + convert between __bfloat16 and float vector types. */ #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_CRYPTO \ @@ -102,7 +111,6 @@ /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add FLOAT128_HW here until we are ready to make -mfloat128 on by default. */ #define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \ - /* | OPTION_MASK_FLOAT16 */ \ | OPTION_MASK_ISEL \ | OPTION_MASK_MODULO \ | OPTION_MASK_P9_MINMAX \ @@ -114,7 +122,6 @@ performance was degraded by it. */ #define OTHER_POWER10_MASKS (OPTION_MASK_MMA \ | OPTION_MASK_PCREL \ - /* | OPTION_MASK_BFLOAT16 */ \ /* | OPTION_MASK_PCREL_OPT */ \ | OPTION_MASK_PREFIXED) @@ -154,8 +161,12 @@ #endif /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ + +/* In the future if 16-bit floating point is enabled by default for ISA 2.7 + (power8), add OPTION_MASK_FLOAT16 and OPTION_MASK_BFLOAT16 to + POWERPC_MASKS. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ - | OPTION_MASK_BFLOAT16 \ + /* | OPTION_MASK_BFLOAT16 */ \ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ @@ -163,6 +174,7 @@ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ + /* | OPTION_MASK_FLOAT16 */ \ | OPTION_MASK_FPRND \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \
