https://gcc.gnu.org/g:b0f0452d01c0caa2a9a4ee211222a1696c1d8bfe
commit b0f0452d01c0caa2a9a4ee211222a1696c1d8bfe Author: Michael Meissner <[email protected]> Date: Wed Oct 22 16:40:49 2025 -0400 Add scalar _Float16 converts. 2025-10-21 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (FP16_HW): New mode iterator. (VFP16_HW): Likewise. (fp16_float_convert): Likewise. (extendhf<mode>2): Add support converting between HFmode and other floating point scalars if we are on power9 or later. (trunc<mode>hf2): Likewise. (extend<FP16_HW:mode><fp16_float_convert:mode>): Likewise. (trunc<fp16_float_convert:mode><FP16_HW:mode>2): Likewise. (float<GPR:mode><FP16_HW:mode>2): Add support converting between HFmode to and from integers. (floatuns<GPR:mode><FP16_HW:mode>2): Likewise. (fix_trunc<FP16_HW:mode><GPR:mode>2): Likewise. (fixuns_trunc<FP16_HW:mode><GPR:mode>2): Likewise. Diff: --- gcc/config/rs6000/float16.md | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 9e3444111ddc..5343f0c730cc 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -61,16 +61,16 @@ (define_insn "*mov<mode>_xxspltiw" [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,wa,?r,?r") (match_operand:FP16 1 "fp16_xxspltiw_constant" "j,eP,j,eP"))] - "" + "TARGET_PREFIXED || operands[1] == CONST0_RTX (<MODE>mode)" { rtx op1 = operands[1]; const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op1); long real_words[1]; if (op1 == CONST0_RTX (<MODE>mode)) - return (vsx_register_operand (operands[0], <MODE>mode) - ? "xxspltib %x0,0" - : "li %0,0"); + return (!vsx_register_operand (operands[0], <MODE>mode) + ? "li %0,0" + : "xxlxor %x0,%x0,%x0"); real_to_target (real_words, rtype, <MODE>mode); operands[2] = GEN_INT (real_words[0]); @@ -78,8 +78,8 @@ ? "xxspltiw %x0,%2" : "pli %0,%2"); } - [(set_attr "type" "vecsimple,vecsimple,*,*") - (set_attr "prefixed" "no,yes,no,yes")]) + [(set_attr "type" "veclogical, vecsimple, *, *") + (set_attr "prefixed" "no, yes, no, yes")]) (define_insn "*mov<mode>_internal" [(set (match_operand:FP16 0 "nonimmediate_operand" @@ -100,12 +100,12 @@ sth%U0%X0 %1,%0 mfvsrwz %0,%x1 mtvsrwz %x0,%1 - xxspltib %x0,0 + xxlxor %x0,%x0,%x0 li %0,0" - [(set_attr "type" "vecsimple, fpload, fpstore, *, load, - store, mtvsr, mfvsr, vecsimple, *") - (set_attr "isa" "*, p9v, p9v, *, *, - *, p8v, p8v, p9v, *")]) + [(set_attr "type" "vecsimple, fpload, fpstore, *, load, + store, mtvsr, mfvsr, veclogical, *") + (set_attr "isa" "*, p9v, p9v, *, *, + *, p8v, p8v, p9v, *")]) ;; Vector duplicate (define_insn "*vecdup<mode>_reg" @@ -120,11 +120,11 @@ [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=wa,wa") (vec_duplicate:<FP16_VECTOR8> (match_operand:FP16 1 "fp16_xxspltiw_constant" "j,eP")))] - "" + "TARGET_PREFIXED || operands[1] == CONST0_RTX (<MODE>mode)" { rtx op1 = operands[1]; if (op1 == CONST0_RTX (<MODE>mode)) - return "xxspltib %x0,0"; + return "xxlxor %x0,%x0,%x0"; const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op1); long real_words[1]; @@ -133,7 +133,7 @@ operands[2] = GEN_INT (real_words[0]); return "xxspltiw %x0,2"; } - [(set_attr "type" "vecperm") + [(set_attr "type" "veclogical,vecperm") (set_attr "prefixed" "*,yes")])
