https://gcc.gnu.org/g:beb3a08c194db6fac4e3fb762dd8c257b5dfbb4b

commit beb3a08c194db6fac4e3fb762dd8c257b5dfbb4b
Author: Michael Meissner <[email protected]>
Date:   Tue Sep 9 15:47:51 2025 -0400

    Add -mbfloat16 switch.
    
    2025-09-09  Michael Meissner  <[email protected]>
    
    gcc/
    
            * config/rs6000/rs6000.cc (rs6000_opt_masks): Print out -mbfloat16.
            * config/rs6000/rs6000.h (TARGET_BFLOAT16): Delete.
            (FP16_SCALAR_P): For bfloat16, also check if power10.
            * config/rs6000/rs6000.opt (-mbfloat16): New switch.

Diff:
---
 gcc/config/rs6000/rs6000.cc  | 1 +
 gcc/config/rs6000/rs6000.h   | 3 +--
 gcc/config/rs6000/rs6000.opt | 4 ++++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 624fe7138703..a350eeca6dbe 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -24568,6 +24568,7 @@ struct rs6000_opt_mask {
 static struct rs6000_opt_mask const rs6000_opt_masks[] =
 {
   { "altivec",                 OPTION_MASK_ALTIVEC,            false, true  },
+  { "bfloat16",                        OPTION_MASK_BFLOAT16,           false, 
true  },
   { "block-ops-unaligned-vsx", OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX,
                                                                false, true  },
   { "block-ops-vector-pair",   OPTION_MASK_BLOCK_OPS_VECTOR_PAIR,
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 7fc074f93905..98c3ae93fa08 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -571,11 +571,10 @@ extern int rs6000_vector_align[];
    convert vector and scalar _Float16 formats, Power10 has instructions to
    convert vector __bfloat16 formats.  */
 #define TARGET_IEEE16          TARGET_P9_VECTOR
-#define TARGET_BFLOAT16                TARGET_POWER10
 
 #define FP16_SCALAR_P(MODE)                                            \
   (((MODE) == HFmode && TARGET_IEEE16)                                 \
-   || ((MODE) == BFmode && TARGET_BFLOAT16))
+   || ((MODE) == BFmode && TARGET_BFLOAT16 && TARGET_POWER10))
 
 /* Whether the various reciprocal divide/square root estimate instructions
    exist, and whether we should automatically generate code for the instruction
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c248f6c890a1..651964f6cc8e 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -646,6 +646,10 @@ mfloat16-gpr-args
 Target Undocumented Var(TARGET_FLOAT16_GPR_ARGS) Init(1) Save
 Pass and return _Float16 and __bfloat16 in GPR registers.
 
+mbfloat16
+Target Undocumented Mask(BFLOAT16) Var(rs6000_isa_flags)
+Enable __bfloat16 support.
+
 ; Documented parameters
 
 -param=rs6000-vect-unroll-limit=

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