[gcc r16-3332] RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh

[Paul-Antoine Arras via Gcc-cvs]

https://gcc.gnu.org/g:4196389cd2dd0e4f612df4a664be9164cbc50989

commit r16-3332-g4196389cd2dd0e4f612df4a664be9164cbc50989
Author: Paul-Antoine Arras <par...@baylibre.com>
Date:   Wed Aug 20 15:24:31 2025 +0200

    RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
    
    Call check_effective_target_riscv_zvfh_ok rather than
    check_effective_target_riscv_zvfh in vx_vf_*run-1-f16.c run tests and ensure
    that they are actually run.
    Also fix remove_options_for_riscv_zvfh.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c: Call
            check_effective_target_riscv_zvfh_ok rather than
            check_effective_target_riscv_zvfh.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c: 
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c: 
Likewise.
            * lib/target-supports.exp (check_effective_target_riscv_zvfh_ok): 
Append
            zvfh instead of v to march.
            (remove_options_for_riscv_zvfh): Remove duplicate and
            call remove_ rather than add_options_for_riscv_z_ext.

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c     | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c     | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c     | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c     | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c     | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c     | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c    | 2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c    | 2 +-
 gcc/testsuite/lib/target-supports.exp                             | 8 ++------
 13 files changed, 14 insertions(+), 18 deletions(-)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
index fd8aa30be17a..a54d9a12ecdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
index 8fd855288993..2289d04e91d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
index e91fd15a5b73..b6d944cf945f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
index ca7e0db17b5b..e9253fe407c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
index b38e8009fd8f..397e2834e29c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
index fef5d7779a28..6d846a23af7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
index 7951d402c1e7..0b4f6e105689 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
index d0def86acc52..acc7aa35ebf9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
index d4c527abd36c..a858d27119b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
index abce2f2c408d..a04bd91213a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
index ddf49d5b2f23..a00d6206fd94 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
index a8749915569a..eeae215c80f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index e8f888525917..b49363caa12b 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2342,7 +2342,7 @@ proc check_effective_target_riscv_zvfh_ok { } {
 
     # check if we can execute vector insns with the given hardware or
     # simulator
-    set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v]
+    set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &zvfh]
     if { [check_runtime ${gcc_march}_zvfh_exec {
        int main()
        {
@@ -2711,10 +2711,6 @@ proc remove_options_for_riscv_ztso { flags } {
     return [remove_options_for_riscv_z_ext ztso $flags]
 }
 
-proc remove_options_for_riscv_zvfh { flags } {
-    return [add_options_for_riscv_z_ext zvfh $flags]
-}
-
 proc add_options_for_riscv_zvbb { flags } {
     return [add_options_for_riscv_z_ext zvbb $flags]
 }
@@ -2728,7 +2724,7 @@ proc add_options_for_riscv_zvfh { flags } {
 }
 
 proc remove_options_for_riscv_zvfh { flags } {
-    return [add_options_for_riscv_z_ext zvfh $flags]
+    return [remove_options_for_riscv_z_ext zvfh $flags]
 }
 
 # Return 1 if the target is ia32 or x86_64.