https://gcc.gnu.org/g:15dc059bd7783de6fc84879664e55e000c09557a
commit r16-3239-g15dc059bd7783de6fc84879664e55e000c09557a
Author: Jan Dubiec <j...@o2.pl>
Date: Sun Aug 17 08:03:33 2025 -0600
[PR target/109324] H8/300: Fix genrecog warnings about operands missing
modes.
This patch fixes genrecog warnings about operands missing modes. This is
done by explicitly specifying modes of operations.
PR target/109324
gcc/ChangeLog:
* config/h8300/addsub.md: Explicitly specify mode for plus
operation.
* config/h8300/jumpcall.md: Explicitly specify modes for eq and
match_operand operations.
* config/h8300/testcompare.md: Explicitly specify modes for eq, ltu
and compare operations.
Diff:
---
gcc/config/h8300/addsub.md | 2 +-
gcc/config/h8300/jumpcall.md | 12 ++++++------
gcc/config/h8300/testcompare.md | 26 +++++++++++++-------------
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/gcc/config/h8300/addsub.md b/gcc/config/h8300/addsub.md
index 32eba9df67aa..f15362594d4f 100644
--- a/gcc/config/h8300/addsub.md
+++ b/gcc/config/h8300/addsub.md
@@ -271,7 +271,7 @@
(match_operand:QHSI 2 "register_operand" "r"))
(match_dup 1)))
(set (match_operand:QHSI 0 "register_operand" "=r")
- (plus (match_dup 1) (match_dup 2)))
+ (plus:QHSI (match_dup 1) (match_dup 2)))
(clobber (reg:CC CC_REG))]
""
{
diff --git a/gcc/config/h8300/jumpcall.md b/gcc/config/h8300/jumpcall.md
index 4e634085130c..44847e4b43ea 100644
--- a/gcc/config/h8300/jumpcall.md
+++ b/gcc/config/h8300/jumpcall.md
@@ -156,7 +156,7 @@
"#"
"&& reload_completed"
[(set (reg:CCZ CC_REG)
- (eq (zero_extract:HSI (match_dup 1) (const_int 1) (match_dup 2))
+ (eq:CCZ (zero_extract:HSI (match_dup 1) (const_int 1) (match_dup 2))
(const_int 0)))
(set (pc)
(if_then_else (match_op_dup 3 [(reg:CCZ CC_REG) (const_int 0)])
@@ -181,7 +181,7 @@
(lshiftrt:SI (match_dup 1) (const_int 16))))
(clobber (reg:CC CC_REG))])
(set (reg:CCZ CC_REG)
- (eq (zero_extract:SI (match_dup 4) (const_int 1) (match_dup 2))
+ (eq:CCZ (zero_extract:SI (match_dup 4) (const_int 1) (match_dup 2))
(const_int 0)))
(set (pc)
(if_then_else (match_op_dup 3 [(reg:CCZ CC_REG) (const_int 0)])
@@ -288,7 +288,7 @@
})
(define_insn "call_insn_<mode>"
- [(call (mem:QI (match_operand 0 "call_insn_operand" "Cr"))
+ [(call (mem:QI (match_operand:P 0 "call_insn_operand" "Cr"))
(match_operand:P 1 "general_operand" "g"))]
"!SIBLING_CALL_P (insn)"
{
@@ -326,7 +326,7 @@
(define_insn "call_value_insn_<mode>"
[(set (match_operand 0 "" "=r")
- (call (mem:QI (match_operand 1 "call_insn_operand" "Cr"))
+ (call (mem:QI (match_operand:P 1 "call_insn_operand" "Cr"))
(match_operand:P 2 "general_operand" "g")))]
"!SIBLING_CALL_P (insn)"
{
@@ -358,7 +358,7 @@
})
(define_insn "sibcall_insn_<mode>"
- [(call (mem:QI (match_operand 0 "call_insn_operand" "Cr"))
+ [(call (mem:QI (match_operand:P 0 "call_insn_operand" "Cr"))
(match_operand:P 1 "general_operand" "g"))]
"SIBLING_CALL_P (insn)"
{
@@ -396,7 +396,7 @@
(define_insn "sibcall_value_insn_<mode>"
[(set (match_operand 0 "" "=r")
- (call (mem:QI (match_operand 1 "call_insn_operand" "Cr"))
+ (call (mem:QI (match_operand:P 1 "call_insn_operand" "Cr"))
(match_operand:P 2 "general_operand" "g")))]
"SIBLING_CALL_P (insn)"
{
diff --git a/gcc/config/h8300/testcompare.md b/gcc/config/h8300/testcompare.md
index 694c9e60d4ea..3b43381e64a8 100644
--- a/gcc/config/h8300/testcompare.md
+++ b/gcc/config/h8300/testcompare.md
@@ -28,7 +28,7 @@
;;
(define_insn ""
[(set (reg:CCZ CC_REG)
- (eq (zero_extract:HSI (match_operand:HSI 0 "register_operand" "r")
+ (eq:CCZ (zero_extract:HSI (match_operand:HSI 0 "register_operand" "r")
(const_int 1)
(match_operand 1 "const_int_operand" "n"))
(const_int 0)))]
@@ -54,7 +54,7 @@
(define_insn "*tsthi_upper"
[(set (reg:CCZN CC_REG)
- (compare (and:HI (match_operand:HI 0 "register_operand" "r")
+ (compare:CCZN (and:HI (match_operand:HI 0 "register_operand" "r")
(const_int -256))
(const_int 0)))]
"reload_completed"
@@ -63,7 +63,7 @@
(define_insn "*tsthi_upper_z"
[(set (reg:CCZ CC_REG)
- (compare (and:HI (match_operand:HI 0 "register_operand" "r")
+ (compare:CCZ (and:HI (match_operand:HI 0 "register_operand" "r")
(const_int -256))
(const_int 0)))]
"reload_completed"
@@ -72,7 +72,7 @@
(define_insn "*tstsi_upper"
[(set (reg:CCZN CC_REG)
- (compare (and:SI (match_operand:SI 0 "register_operand" "r")
+ (compare:CCZN (and:SI (match_operand:SI 0 "register_operand" "r")
(const_int -65536))
(const_int 0)))]
"reload_completed"
@@ -81,7 +81,7 @@
(define_insn "*cmp<mode>_c"
[(set (reg:CCC CC_REG)
- (ltu (match_operand:QHSI 0 "h8300_dst_operand" "rQ")
+ (ltu:CCC (match_operand:QHSI 0 "h8300_dst_operand" "rQ")
(match_operand:QHSI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
{
@@ -97,7 +97,7 @@
(define_insn "*cmpqi_z"
[(set (reg:CCZ CC_REG)
- (eq (match_operand:QI 0 "h8300_dst_operand" "rQ")
+ (eq:CCZ (match_operand:QI 0 "h8300_dst_operand" "rQ")
(match_operand:QI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
{ return "cmp.b %X1,%X0"; }
@@ -105,7 +105,7 @@
(define_insn "*cmphi_z"
[(set (reg:CCZ CC_REG)
- (eq (match_operand:HI 0 "h8300_dst_operand" "rQ")
+ (eq:CCZ (match_operand:HI 0 "h8300_dst_operand" "rQ")
(match_operand:HI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
{ return "cmp.w %T1,%T0"; }
@@ -113,7 +113,7 @@
(define_insn "*cmpsi_z"
[(set (reg:CCZ CC_REG)
- (eq (match_operand:SI 0 "h8300_dst_operand" "rQ")
+ (eq:CCZ (match_operand:SI 0 "h8300_dst_operand" "rQ")
(match_operand:SI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
{ return "cmp.l %S1,%S0"; }
@@ -121,7 +121,7 @@
(define_insn "*cmpqi"
[(set (reg:CC CC_REG)
- (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
+ (compare:CC (match_operand:QI 0 "h8300_dst_operand" "rQ")
(match_operand:QI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
"cmp.b %X1,%X0"
@@ -129,7 +129,7 @@
(define_insn "*cmphi"
[(set (reg:CC CC_REG)
- (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
+ (compare:CC (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
(match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
"reload_completed"
{
@@ -150,7 +150,7 @@
(define_insn "cmpsi"
[(set (reg:CC CC_REG)
- (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
+ (compare:CC (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
(match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
"reload_completed"
{
@@ -176,7 +176,7 @@
(define_peephole2
[(match_scratch:QHSI 1 "r")
(set (reg:CC CC_REG)
- (compare (match_operand:QHSI 0 "memory_operand" "")
+ (compare:CC (match_operand:QHSI 0 "memory_operand" "")
(const_int 0)))]
"!mode_dependent_address_p (XEXP (operands[0], 0), MEM_ADDR_SPACE
(operands[0]))"
[(parallel [(set (reg:CCZN CC_REG) (compare:CCZN (match_dup 0) (const_int
0)))
@@ -187,7 +187,7 @@
(define_peephole2
[(match_scratch:QHSI 1 "r")
(set (reg:CC CC_REG)
- (compare (match_operand:QHSI 0 "memory_operand" "")
+ (compare:CC (match_operand:QHSI 0 "memory_operand" "")
(const_int 0)))]
"mode_dependent_address_p (XEXP (operands[0], 0), MEM_ADDR_SPACE
(operands[0]))"
[(parallel [(set (match_dup 1) (match_dup 0)) (clobber (reg:CC CC_REG))])
