[gcc r16-2451] RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.

[Robin Dapp via Gcc-cvs]

https://gcc.gnu.org/g:4b62bd519a852af8f69b077ba7b0ed531f4a14c5

commit r16-2451-g4b62bd519a852af8f69b077ba7b0ed531f4a14c5
Author: Robin Dapp <rd...@ventanamicro.com>
Date:   Mon Jul 21 15:32:09 2025 +0200

    RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
    
    This patch fixes the vf_vfmacc-run-1-f16.c test failures on rv32
    by adding zvfh requirements as well as options to the test and
    the target harness.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c:
            Add zvfh requirements and options.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c:
            Ditto.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c:
            Ditto.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c:
            Ditto.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c:
            Ditto.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c:
            Ditto.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c:
            Ditto.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c:
            Ditto.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c:
            Ditto.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c:
            Ditto.
            * lib/target-supports.exp: Add zvfh options.

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c      | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c      | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c      | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c      | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c     | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c     | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c     | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c     | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c     | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c     | 6 +++++-
 gcc/testsuite/lib/target-supports.exp                             | 8 ++++++++
 11 files changed, 58 insertions(+), 10 deletions(-)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
index 982dd9736acc..fd8aa30be17a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
index 400bbcd1d79f..8fd855288993 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
index 21c1860c0f1c..e91fd15a5b73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
index 163b5bd21b42..ca7e0db17b5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
index 71f350f74e22..b38e8009fd8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
index e252e0dc21a3..fef5d7779a28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
index 439fd3e50560..7951d402c1e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
index b9d66bafeadc..d0def86acc52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 #include "vf_mulop_data.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
index d78cf7384a43..d4c527abd36c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
index 6422bbaa4963..abce2f2c408d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 30d12a975748..018a6d3a764d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2697,6 +2697,14 @@ proc remove_options_for_riscv_zvbb { flags } {
     return [add_options_for_riscv_z_ext zvbb $flags]
 }
 
+proc add_options_for_riscv_zvfh { flags } {
+    return [add_options_for_riscv_z_ext zvfh $flags]
+}
+
+proc remove_options_for_riscv_zvfh { flags } {
+    return [add_options_for_riscv_z_ext zvfh $flags]
+}
+
 # Return 1 if the target is ia32 or x86_64.
 
 proc check_effective_target_x86 { } {