https://gcc.gnu.org/g:59d1bcfe4713965941e6eec13b540c17c7ff1a14

commit 59d1bcfe4713965941e6eec13b540c17c7ff1a14
Author: Michael Meissner <meiss...@linux.ibm.com>
Date:   Wed Jul 9 01:54:45 2025 -0400

    PR target/117251: Improve vector or to vector nand fusion
    
    See the following post for a complete explanation of what the patches
    for PR target/117251:
    
     * https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html
    
    This is patch #41 of 45 to generate the 'XXEVAL' instruction on power10
    and power11 instead of using the Altivec 'VOR' instruction feeding into
    'VNAND'.  The 'XXEVAL' instruction can use all 64 vector registers,
    instead of the 32 registers that traditional Altivec vector
    instructions use.  By allowing all of the vector registers to be used,
    it reduces the amount of spilling that a large benchmark generated.
    
    Currently the following code:
    
            vector int a, b, c, d;
            a = ~ ((c | d) & b);
    
    Generates:
    
            vor    t,c,d
            vnand  a,t,b
    
    Now in addition with this patch, if the arguments or result is
    allocated to a traditional FPR register, the GCC compiler will now
    generate the following code instead of adding vector move instructions:
    
            xxeval a,b,c,248
    
    Since fusion using 2 Altivec instructions is slightly faster than using
    the 'XXEVAL' instruction we prefer to generate the Altivec instructions
    if we can.  In addition, because 'XXEVAL' is a prefixed instruction, it
    possibly might generate an extra NOP instruction to align the 'XXEVAL'
    instruction.
    
    I have tested these patches on both big endian and little endian
    PowerPC servers, with no regressions.  Can I check these patchs into
    the trunk?
    
    2025-07-09  Michael Meissner  <meiss...@linux.ibm.com>
    
    gcc/
    
            PR target/117251
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support
            to generate vector or => nand fusion if XXEVAL is supported.

Diff:
---
 gcc/config/rs6000/fusion.md    | 15 +++++++++------
 gcc/config/rs6000/genfusion.pl |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 01b7fda17ecc..39b586918c17 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2435,20 +2435,23 @@
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vor -> vnand
 (define_insn "*fuse_vor_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
-        (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" 
"v,v,v,v")
-                          (match_operand:VM 1 "altivec_register_operand" 
"v,v,v,v")))
-                 (not:VM (match_operand:VM 2 "altivec_register_operand" 
"v,v,v,v"))))
-   (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+  [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+        (ior:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" 
"v,v,v,wa,v")
+                          (match_operand:VM 1 "vector_fusion_operand" 
"v,v,v,wa,v")))
+                 (not:VM (match_operand:VM 2 "vector_fusion_operand" 
"v,v,v,wa,v"))))
+   (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
   "(TARGET_P10_FUSION)"
   "@
    vor %3,%1,%0\;vnand %3,%3,%2
    vor %3,%1,%0\;vnand %3,%3,%2
    vor %3,%1,%0\;vnand %3,%3,%2
+   xxeval %x3,%x2,%x1,%x0,248
    vor %4,%1,%0\;vnand %3,%4,%2"
   [(set_attr "type" "fused_vector")
    (set_attr "cost" "6")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "prefixed" "*,*,*,yes,*")
+   (set_attr "isa" "*,*,*,xxeval,*")])
 
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vorc -> vnand
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index d4965b6df864..86bca81286ca 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -255,6 +255,7 @@ sub gen_logical_addsubf
       "vorc_vnand"  => 244,
       "veqv_vnand"  => 246,
       "vnor_vnand"  => 247,
+      "vor_vnand"   => 248,
     );
 
     KIND: foreach $kind ('scalar','vector') {

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