https://gcc.gnu.org/g:b14b34c56ef8da774c9e6352c39907dd7fec783b
commit b14b34c56ef8da774c9e6352c39907dd7fec783b
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Jul 9 01:51:28 2025 -0400
PR target/117251: Improve vector andc to vector eqv fusion
See the following post for a complete explanation of what the patches
for PR target/117251:
* https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html
This is patch #33 of 45 to generate the 'XXEVAL' instruction on power10
and power11 instead of using the Altivec 'VANDC' instruction feeding
into 'VEQV'. The 'XXEVAL' instruction can use all 64 vector registers,
instead of the 32 registers that traditional Altivec vector
instructions use. By allowing all of the vector registers to be used,
it reduces the amount of spilling that a large benchmark generated.
Currently the following code:
vector int a, b, c, d;
a = ~ ((c & ~ d) ^ b);
Generates:
vandc t,c,d
veqv a,t,b
Now in addition with this patch, if the arguments or result is
allocated to a traditional FPR register, the GCC compiler will now
generate the following code instead of adding vector move instructions:
xxeval a,b,c,210
Since fusion using 2 Altivec instructions is slightly faster than using
the 'XXEVAL' instruction we prefer to generate the Altivec instructions
if we can. In addition, because 'XXEVAL' is a prefixed instruction, it
possibly might generate an extra NOP instruction to align the 'XXEVAL'
instruction.
I have tested these patches on both big endian and little endian
PowerPC servers, with no regressions. Can I check these patchs into
the trunk?
2025-07-09 Michael Meissner <meiss...@linux.ibm.com>
gcc/
PR target/117251
* config/rs6000/fusion.md: Regenerate.
* config/rs6000/genfusion.pl (gen_logical_addsubf): Add support
to generate vector andc => eqv fusion if XXEVAL is supported.
Diff:
---
gcc/config/rs6000/fusion.md | 15 +++++++++------
gcc/config/rs6000/genfusion.pl | 1 +
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index dd8401d48228..e3d9f7376a8d 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2204,20 +2204,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> veqv
(define_insn "*fuse_vandc_veqv"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %3,%1,%0\;veqv %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,210
vandc %4,%1,%0\;veqv %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,xxeval,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> veqv
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index d89e78d4da03..3a603eb09675 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -247,6 +247,7 @@ sub gen_logical_addsubf
"vorc_vxor" => 180,
"vorc_vor" => 191,
"vandc_vnor" => 208,
+ "vandc_veqv" => 210,
);
KIND: foreach $kind ('scalar','vector') {
