https://gcc.gnu.org/g:a09b415b87cd98e3a4f3e197ad4e9e67a335c1d4
commit r16-2117-ga09b415b87cd98e3a4f3e197ad4e9e67a335c1d4
Author: Pan Li <pan2...@intel.com>
Date: Tue Jul 8 10:46:29 2025 +0800
RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
The rv32 doesn't support __uint128, and then we will have
error like below during test.
error: '__int128' is not supported on this target.
Thus, we disable the uint128_t related test when rv32.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat/sat_arith.h: Add xlen check for
uint128_t.
* gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c: Enable
run test for rv64 only.
* gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c: Ditto.
* gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c: Ditto.
* gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
gcc/testsuite/gcc.target/riscv/sat/sat_arith.h | 4 +++-
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c | 2 +-
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c | 2 +-
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c | 2 +-
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c | 2 +-
5 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
index 3de89f47ae09..7e2c93e5af3f 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
@@ -4,7 +4,9 @@
#include <stdint-gcc.h>
#include <stdbool.h>
-typedef __uint128_t uint128_t;
+#if __riscv_xlen == 64
+typedef unsigned __int128 uint128_t;
+#endif
/******************************************************************************/
/* Saturation Add (unsigned and signed)
*/
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
index 395a4cb060cf..79f62973af3d 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
/* { dg-additional-options "-std=c99" } */
#include "sat_arith.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c
index 3c8b72806a4e..e5a94627fa00 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
/* { dg-additional-options "-std=c99" } */
#include "sat_arith.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c
index e5572de85350..cbe2a221791d 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
/* { dg-additional-options "-std=c99" } */
#include "sat_arith.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c
index 2e9c39a20faa..1f54c303fbb2 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
/* { dg-additional-options "-std=c99" } */
#include "sat_arith.h"
