https://gcc.gnu.org/g:dab5951af891c58aa4dd60755edb49df882b680a
commit r16-2102-gdab5951af891c58aa4dd60755edb49df882b680a Author: Robin Dapp <rd...@ventanamicro.com> Date: Tue Jul 8 11:35:12 2025 +0200 RISC-V: Do not use vsetivli for THeadVector. In emit_vlmax_insn_lra we use a vsetivli for an immediate AVL. XTHeadVector does not support this, so guard appropriately. PR target/120461 gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Do not emit vsetivli for XTHeadVector. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/pr120461.c: New test. Diff: --- gcc/config/riscv/riscv-v.cc | 2 +- gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index a5ab8dd4e2fe..22d194909cfa 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -408,7 +408,7 @@ emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) gcc_assert (!can_create_pseudo_p ()); machine_mode mode = GET_MODE (ops[0]); - if (imm_avl_p (mode)) + if (imm_avl_p (mode) && !TARGET_XTHEADVECTOR) { /* Even though VL is a real hardreg already allocated since it is post-RA now, we still gain benefits that we emit diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c new file mode 100644 index 000000000000..69391570970f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=xt-c920 -mrvv-vector-bits=zvl -fzero-call-used-regs=all" */ + +void +foo () +{}