The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
7363e569418e... Refactor record_function_versions.
It previously pointed to:
1d5cfe644cd2... Refactor record_function_versions.
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------
1d5cfe6... Refactor record_function_versions.
f7d3710... [RISC-V][PR target/118886] Refine when two insns are signal
ef87b0d... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
218cccc... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
c09ee71... [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTE
82b78b6... ext-dce: Don't refine live width with SUBREG mode if !TRULY
9576acb... [RISC-V] Correct CFA notes for stack-clash protection [PR12
d96b59c... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
780792d... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
fdc172e... RISC-V: Reconcile the existing test due to cost model chang
076b6ce... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
1c66ca2... RISC-V: Ignore -Oz for most rvv testcase [NFC]
6f0e70e... RISC-V: Primary vector pipeline model for sifive 7 series
a91fa2a... RISC-V: Adding B ext, fp16 and missing scalar instruction t
3026828... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
e67bd29... RISC-V: Refactor the function bitmap_union_of_preds_with_en
ce4e56e... RISC-V: Add pipeline-checker script
040d02c... [sanitizer_common] Fix build on ppc64+musl (#120036)
e520ad3... [RISC-V][PR target/119971] Avoid losing shift count masking
20e57a6... RISC-V: update prepare_ternary_operands to handle vector-sc
eef3fd5... RISC-V: Fix build issue
64af55c... RISC-V: Add comment and reorder the the include files in ri
95c6127... RISC-V: Add Profiles RVA/B23S64 support.
cbdf794... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
d08eceb... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
21c82c4... Fixup dropping REG_EQUAL note in ext-dce
8712876... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
68deb26... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
fe2c046... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
2e8d2d1... [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit host
4e879da... [committed][PR rtl-optimization/120550] Drop REG_EQUAL note
4e8970b... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
44ac6ec... RISC-V: Fix ICE for expand_select_vldi [PR120652]
1db0924... [RISC-V] Force several tests to use rocket tuning
ac124f4... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
b319ccf... RISC-V: Add test for vec_duplicate + vminu.vv combine case
dddb4ea... RISC-V: Add test for vec_duplicate + vminu.vv combine case
d384bfb... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
209297c... RISC-V: Add generic tune as default.
bff5289... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
f6691d5... RISC-V: Adding cost model for zilsd
f2192cd... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
0b1f503... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
105cb2d... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
e2f9329... [PATCH v1] RISC-V: Use scratch reg for loop control
b11a59c... RISC-V: Add -fno-pie flags to testcases
d683e12... RISC-V: Refine VX combine test case 0 to avoid code duplica
b5c60ee... RISC-V: Update Profiles string in RV23.
5298cd8... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
529fb26... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
bab882c... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
a80b68c... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
2abc798... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
d6823d1... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
b646f8e... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
5f5b57e... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
b7f9bc1... RISC-V: Prevent speculative vsetvl insn scheduling
8bf791d... RISC-V: Add patterns for vector-scalar negate-(multiply-add
f34e6ea... RISC-V: testsuite: fix an obvious build error
4c63893... [RISC-V] Fix ICE due to splitter emitting constant loads di
e3ada8e... RISC-V: Regen riscv-ext.texi [NFC]
64b8dee... RISC-V: Add test for vec_duplicate + vremu.vv combine case
6250399... RISC-V: Add test for vec_duplicate + vremu.vv combine case
2e3b57d... RISC-V: Reconcile the existing test for vremu.vx combine
1af3a0a... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
65b255f... [RISC-V] Enable more if-conversion on RISC-V
725444b... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
a4bcae5... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
b48ccf6... RISC-V: Reconcile the existing test for vrem.vx combine
852bbab... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
3111145... RISC-V: frm/mode-switch: robustify call_insn backtracking [
e9f1bc4... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
807bdaa... RISC-V: frm/mode-switch: remove dubious frm edge insertion
2b418bd... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
e47d402... [RISC-V] Handle 32bit operands in condition for conditional
38f54b2... [to-be-committed][RISC-V] Handle 32bit operands in conditio
f633e6f... RISC-V: Reconcile the existing test for vdivu.vx combine
f47952a... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
f34bc1e... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
7e0e570... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
523071d... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
5dd9e41... [RISC-V] Improve signed division by 2^n
2b2971f... RISC-V: Don't use structured binding in riscv-common.cc
29c38bf... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
4a89441... [RISC-V] Improve sequences to generate -1, 1 in some cases.
1787f1a... RISC-V: Support Ssu64xl extension.
7d13811... RISC-V: Support Sstvecd extension.
7eb7f4f... RISC-V: Support Sstvala extension.
f17303c... RISC-V: Support Sscounterenw extension.
f58bec2... RISC-V: Support Ssccptr extension.
11d80e3... RISC-V: Support Smrnmi extension.
d9b60c3... RISC-V: Support Sm/scsrind extensions.
3ba8b08... RISC-V: Update extension defination.
1253ab8... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
bed8b67... [PATCH v2] RISC-V: Add svbare extension.
90c8424... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
087e777... RISC-V: Add Shlcofideleg extension.
6f86911... RISC-V: Reconcile the existing test for vdiv.vx combine
a1bc833... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
dcf0e76... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
a16aae2... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
03d5c7a... RISC-V: Use helper function to get FPR to VR move cost
f7a94e5... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
e313f01... [PATCH] RISC-V: Add smcntrpmf extension.
21fad71... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
d581dfe... RISC-V: Implement full-featured iterator for riscv_subset_l
cf48dab... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
f501c35... RISC-V: Fix line too long format issue for autovect.md [NFC
00da44f... RISC-V: Add test cases for avg_ceil vaadd implementation
580b98e... RISC-V: Reconcile the existing test for avg_ceil
7926027... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
ae57b36... RISC-V: Add minimal support of double trap extension 1.0
c81295d... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
1a15db2... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
87b360b... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
ef85803... RISC-V: Avoid division by zero in check_builtin_call [PR120
9f09bc5... RISC-V: Add test cases for avg_floor vaadd implementation
474b25d... RISC-V: Reconcile the existing test for avg_floor
85805f1... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
6bece84... [RISC-V] Add andi+bclr synthesis
2112e84... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
6cee635... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
9b0d303... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
c97e413... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
3e7ab47... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
b2e7fd2... [RISC-V] shift+and+shift for logical and synthesis
aba6435... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
cfb49a1... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
be69c39... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
736bdd7... RISC-V: Support CPUs in -march.
15cc995... RISC-V: Add autovec mode param.
cb1ec11... RISC-V: Default-initialize variable.
0e627a6... RISC-V: Fix some dynamic LMUL costing.
129a474... [RISC-V] Clear both upper and lower bits using 3 shifts
2828c84... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
a02a5bc... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
634a4be... [RISC-V] Clear high or low bits using shift pairs
f7e1e41... [RISC-V] Improve (x << C1) + C2 split code
1384d5e... [RISC-V][PR target/120368] Fix 32bit shift on rv64
8045904... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
16eca41... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
726454e... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
4787ad2... [RISC-V] Infrastructure of synthesizing logical AND with co
78a47aa... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
208a74e... [PATCH v2 1/2] The following changes enable P8700 processor
7f8c70a... [RISC-V] Avoid multiple assignments to output object
d641082... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
4935cb1... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
31e78af... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
7d174b9... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
dc775ce... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
891d92d... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
86049f5... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
2da2451... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
1313b33... [committed][RISC-V][PR target/120333] Remove bogus bext pat
7b6a39a... [RISC-V] Fix false positive from Wuninitialized
03e297f... RISC-V: Fix the warning of temporary object dangling refere
ec6b06a... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
5a6d03f... RISC-V: Support Zilsd code gen
fd457d6... RISC-V: Add new operand constraint: cR
5159c19... [RISC-V] Fix ICE due to bogus use of gen_rtvec
8010f98... [RISC-V] Avoid setting output object more than once in IOR/
99d801c... RISC-V: Since the loop increment i++ is unreachable, the lo
6e73320... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
84adfa2... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
49278dd... Make end_sequence return the insn sequence
9a8ca2f... RISC-V: Reuse test name for vx combine test data [NFC]
76ecd76... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
13a6e9f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
1a93ea8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
04f07ee... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
c0cb19a... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
7195b88... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
8776c19... RISC-V: Adjust vx combine test case to avoid name conflict
f6ae7c8... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
6785ad3... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
103da6a... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
5e6cb89... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
fa7576e... RISC-V: Add augmented hypervisor series extensions.
b0fb9ba... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
a4d3735... RISC-V: Regen riscv-ext.opt.urls
8b77ff6... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
1931c49... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
d5d13d9... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
1c2a373... RISC-V: Introduce riscv_ext_info_t to hold extension metada
4d7dafb... RISC-V: Adjust riscv_can_inline_p
ac1cfc5... RISC-V: Generate extension table in documentation from risc
dff806e... RISC-V: Use riscv-ext.def to generate target options and va
f63e8d3... RISC-V: Introduce riscv-ext*.def to define extensions
194d03f... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
24f53c2... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
9df770e... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
543db94... RISC-V: Support for zilsd and zclsd extensions.
e63c207... testsuite: Fix RISC-V arch-52.c format issue.
e887f88... RISC-V: Support RISC-V Profiles 23.
7f87d18... RISC-V: Support RISC-V Profiles 20/22.
7866e62... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
ea263e8... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
c118441... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
621d370... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
1072dae... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
3045c15... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
e6cdd98... RISC-V: Separate the test running of rvv vx_vf
8ad5762... [RISC-V][PR target/120137][PR target/120154] Don't create o
1953b5e... [PATCH] RISC-V: Minimal support for zama16b extension.
832d5bc... [RISC-V] Avoid unnecessary andi with -1 argument
71b1760... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
a67f729... [PATCH] RISC-V: Recognized svadu and svade extension
65d4610... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
9d9135a... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
11b0993... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
39e8197... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
c5d906d... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
2ee71e5... RISC-V: Add gr2vr cost helper function
9b6166d... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
f792a2e... [RISC-V][PR target/119971] Avoid losing shift count masking
b4ff83a... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
6b9a261... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
10057e3... [V2][RISC-V] Trivial permutation constant derivation
1cc79df... [RISC-V] Adjust rvv tests after recent jump threading chang
f597a59... [PATCH] RISC-V: Implment H modifier for printing the next r
f7d0410... [to-be-committed][RISC-V] Adjust testcases and finish regis
1982909... RISC-V: Remove unnecessary frm restore volatile define_insn
5179fed... RISC-V: Allow different dynamic floating point mode to be m
5561ed0... RISC-V: Fix missing implied Zicsr from Zve32x
2e800ed... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
8633535... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
2bf7f42... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
f789cda... RISC-V: Extract vector stepped for expand_const_vector [NFC
11dcc49... RISC-V: Extract vector duplicate for expand_const_vector [N
8146b6e... RISC-V: Extract vec_series for expand_const_vector [NFC]
84be3be... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
e7e5a11... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
3cbe409... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
9849e5f... [riscv] vec_dup immediate constants in pred_broadcast expan
f8d5c0a... [RISC-V][PR target/119865] Don't free ggc allocated memory
512a79e... [RISC-V][PR target/118410] Improve code generation for some
9c84211... [RISC-V] Fix missed bext discovery
dd04c59... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
ec8bf88... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
8b34e03... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
7363e56... Refactor record_function_versions.
477d40b... [RISC-V][PR target/118886] Refine when two insns are signal
7c41709... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
09f1fdd... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
102e915... [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTE
76d99d9... [RISC-V] Correct CFA notes for stack-clash protection [PR12
c20878b... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
de5e9aa... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
927d0cb... RISC-V: Reconcile the existing test due to cost model chang
f6f8088... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
4c823d9... RISC-V: Ignore -Oz for most rvv testcase [NFC]
13b49dd... RISC-V: Primary vector pipeline model for sifive 7 series
71cc3ca... RISC-V: Adding B ext, fp16 and missing scalar instruction t
0be8dc1... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
6ce0821... RISC-V: Refactor the function bitmap_union_of_preds_with_en
101b601... RISC-V: Add pipeline-checker script
822bd8f... [sanitizer_common] Fix build on ppc64+musl (#120036)
5ad1aa3... [RISC-V][PR target/119971] Avoid losing shift count masking
058acd7... RISC-V: update prepare_ternary_operands to handle vector-sc
14c1c41... RISC-V: Fix build issue
329a20b... RISC-V: Add comment and reorder the the include files in ri
30bc81d... RISC-V: Add Profiles RVA/B23S64 support.
7579e0c... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
a0cca39... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
0378e1e... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
26cde1e... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
28a7e66... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
5ccee56... [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit host
30e7306... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
6c397a7... RISC-V: Fix ICE for expand_select_vldi [PR120652]
4431d24... [RISC-V] Force several tests to use rocket tuning
2ea35c1... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
7ec4372... RISC-V: Add test for vec_duplicate + vminu.vv combine case
1b7fcb4... RISC-V: Add test for vec_duplicate + vminu.vv combine case
34c5807... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
d2b21c2... RISC-V: Add generic tune as default.
3becefc... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
f4beb34... RISC-V: Adding cost model for zilsd
16a379b... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
7ad53e8... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
b7ccbdc... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
a97eb08... [PATCH v1] RISC-V: Use scratch reg for loop control
9fe9f65... RISC-V: Add -fno-pie flags to testcases
5abb21b... RISC-V: Refine VX combine test case 0 to avoid code duplica
9f15440... RISC-V: Update Profiles string in RV23.
05bc63f... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
a0d1d0c... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
4af1a95... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
31baabf... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
0363f53... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
b0d572c... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
308422b... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
c545dd7... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
48eaa96... RISC-V: Prevent speculative vsetvl insn scheduling
ec9f7a5... RISC-V: Add patterns for vector-scalar negate-(multiply-add
7469cb5... RISC-V: testsuite: fix an obvious build error
01bbac9... RISC-V: Regen riscv-ext.texi [NFC]
e72e3b9... RISC-V: Add test for vec_duplicate + vremu.vv combine case
1b74e83... RISC-V: Add test for vec_duplicate + vremu.vv combine case
0cb8e0f... RISC-V: Reconcile the existing test for vremu.vx combine
3a987c7... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
dc318d1... [RISC-V] Enable more if-conversion on RISC-V
c3c93b3... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
19ad8d1... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
d981ce1... RISC-V: Reconcile the existing test for vrem.vx combine
0a7f235... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
3770993... RISC-V: frm/mode-switch: robustify call_insn backtracking [
64b1aa9... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
2d2ea24... RISC-V: frm/mode-switch: remove dubious frm edge insertion
41313ac... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
96541e6... [RISC-V] Handle 32bit operands in condition for conditional
2283c7e... [to-be-committed][RISC-V] Handle 32bit operands in conditio
71cc200... RISC-V: Reconcile the existing test for vdivu.vx combine
275b04c... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
cffd80f... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
bcdf931... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
27bee9e... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
7e1fbe7... [RISC-V] Improve signed division by 2^n
8af974e... RISC-V: Don't use structured binding in riscv-common.cc
7c46682... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
957f90a... [RISC-V] Improve sequences to generate -1, 1 in some cases.
a8537f7... RISC-V: Support Ssu64xl extension.
8b3cd36... RISC-V: Support Sstvecd extension.
596f77f... RISC-V: Support Sstvala extension.
ef7643f... RISC-V: Support Sscounterenw extension.
bb1262a... RISC-V: Support Ssccptr extension.
a6a08cd... RISC-V: Support Smrnmi extension.
883e1d8... RISC-V: Support Sm/scsrind extensions.
3454cda... RISC-V: Update extension defination.
ac488b6... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
05a5edf... [PATCH v2] RISC-V: Add svbare extension.
521f66a... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
2626c79... RISC-V: Add Shlcofideleg extension.
e77de75... RISC-V: Reconcile the existing test for vdiv.vx combine
0eed140... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
d712389... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
c89fb82... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
3341d68... RISC-V: Use helper function to get FPR to VR move cost
8db0209... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
b909545... [PATCH] RISC-V: Add smcntrpmf extension.
4f4e95f... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
4fc2870... RISC-V: Implement full-featured iterator for riscv_subset_l
f483250... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
4e64eea... RISC-V: Fix line too long format issue for autovect.md [NFC
854c64a... RISC-V: Add test cases for avg_ceil vaadd implementation
a056201... RISC-V: Reconcile the existing test for avg_ceil
c58ba0a... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
672d63a... RISC-V: Add minimal support of double trap extension 1.0
37a01a9... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
67f43b2... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
3e7b7fe... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
c0bd9e5... RISC-V: Avoid division by zero in check_builtin_call [PR120
e42582f... RISC-V: Add test cases for avg_floor vaadd implementation
2af6dd9... RISC-V: Reconcile the existing test for avg_floor
b02fdf3... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
2cfc802... [RISC-V] Add andi+bclr synthesis
014f336... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
88dd4a6... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
4a8ee4e... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
0eb7c72... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
5f22320... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
d9ce8e5... [RISC-V] shift+and+shift for logical and synthesis
5eff5f4... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
4f9c151... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
a76c032... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
dc2342a... RISC-V: Support CPUs in -march.
d8e1279... RISC-V: Add autovec mode param.
02758bf... RISC-V: Default-initialize variable.
48e4aed... RISC-V: Fix some dynamic LMUL costing.
8c5d12e... [RISC-V] Clear both upper and lower bits using 3 shifts
79854f9... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
4ead2b0... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
cba7674... [RISC-V] Clear high or low bits using shift pairs
fa0d12f... [RISC-V] Improve (x << C1) + C2 split code
ca792e2... [RISC-V][PR target/120368] Fix 32bit shift on rv64
54f065e... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
ac3460d... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
8e8facb... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
d93e4e5... [RISC-V] Infrastructure of synthesizing logical AND with co
ba16939... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
4c6285f... [PATCH v2 1/2] The following changes enable P8700 processor
eda6b3e... [RISC-V] Avoid multiple assignments to output object
dc4f8e8... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
b13bb6a... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
81734e7... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
323993b... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
c38b9b8... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
469cc6c... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
cec32c2... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
f6327e6... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
ab141c0... [committed][RISC-V][PR target/120333] Remove bogus bext pat
ca3b668... [RISC-V] Fix false positive from Wuninitialized
55085ab... RISC-V: Fix the warning of temporary object dangling refere
fc618ec... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
77ea0ac... RISC-V: Support Zilsd code gen
c36c104... RISC-V: Add new operand constraint: cR
de9601a... [RISC-V] Fix ICE due to bogus use of gen_rtvec
c14b79c... [RISC-V] Avoid setting output object more than once in IOR/
5d221ae... RISC-V: Since the loop increment i++ is unreachable, the lo
cca0dce... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
46c3d92... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
a538b05... Make end_sequence return the insn sequence
51d3403... RISC-V: Reuse test name for vx combine test data [NFC]
c10fe8f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
2f312a4... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
52a93e4... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
3b38a3f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
b02e980... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
b51a35c... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
b79bf32... RISC-V: Adjust vx combine test case to avoid name conflict
0ae5ea9... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
1c91ecf... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
19dbfce... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
f74b7cc... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
4ad5162... RISC-V: Add augmented hypervisor series extensions.
1d459f6... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
89e5968... RISC-V: Regen riscv-ext.opt.urls
98d34e3... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
7d20250... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
1151782... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
13c9dc3... RISC-V: Introduce riscv_ext_info_t to hold extension metada
e4af132... RISC-V: Adjust riscv_can_inline_p
0c85dfe... RISC-V: Generate extension table in documentation from risc
ec13b92... RISC-V: Use riscv-ext.def to generate target options and va
991a5b5... RISC-V: Introduce riscv-ext*.def to define extensions
f841fc0... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
2d190e7... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
197e4a8... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
423a6fc... RISC-V: Support for zilsd and zclsd extensions.
091b0a7... testsuite: Fix RISC-V arch-52.c format issue.
f299534... RISC-V: Support RISC-V Profiles 23.
762080c... RISC-V: Support RISC-V Profiles 20/22.
4679326... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
665c8e3... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
c58e7cb... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
f1ddbef... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
07d884d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
c9a4e7b... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
a0cef8c... RISC-V: Separate the test running of rvv vx_vf
f8d665b... [RISC-V][PR target/120137][PR target/120154] Don't create o
9bdbf2c... [PATCH] RISC-V: Minimal support for zama16b extension.
6519c42... [RISC-V] Avoid unnecessary andi with -1 argument
a85d3aa... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
d053780... [PATCH] RISC-V: Recognized svadu and svade extension
c25cb94... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
fae6884... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
77b4d0b... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
67fc086... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
074b97c... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
cf9debc... RISC-V: Add gr2vr cost helper function
3dbde19... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
ed28056... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
14ee335... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
4bd0c4d... [V2][RISC-V] Trivial permutation constant derivation
739b45a... [RISC-V] Adjust rvv tests after recent jump threading chang
230e928... [PATCH] RISC-V: Implment H modifier for printing the next r
6021cda... [to-be-committed][RISC-V] Adjust testcases and finish regis
832289e... RISC-V: Remove unnecessary frm restore volatile define_insn
26a7c6c... RISC-V: Allow different dynamic floating point mode to be m
67fb8a5... RISC-V: Fix missing implied Zicsr from Zve32x
bfd52bc... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
ddbb041... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
9fdcd6b... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
d79f2cf... RISC-V: Extract vector stepped for expand_const_vector [NFC
c5efbcc... RISC-V: Extract vector duplicate for expand_const_vector [N
1b34877... RISC-V: Extract vec_series for expand_const_vector [NFC]
2cc19b6... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
e7eebae... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
d05ffa6... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
b5f4ff6... [riscv] vec_dup immediate constants in pred_broadcast expan
99f2e82... [RISC-V][PR target/119865] Don't free ggc allocated memory
327b6ed... [RISC-V][PR target/118410] Improve code generation for some
693cba2... [RISC-V] Fix missed bext discovery
48208b7... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
1cbc416... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
b8ae77a... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
ea99ca7... Daily bump. (*)
799dfe7... c++: -Wtemplate-body and tentative parsing [PR120575] (*)
433fcdb... ada: Fix alignment violation for chain of aligned and misal (*)
7b4e397... ada: Fix selection of Finalize subprogram in untagged case (*)
e6e1d88... ada: Fix inefficient Unchecked_Conversion to large array ty (*)
992fb2a... ada: Improved error message when size of descendant type ex (*)
216fc3b... ada: Fix error on Designated_Storage_Model with extensions (*)
9fae682... Daily bump. (*)
f9c4314... c++: Fix a pasto in the PR120471 fix [PR120940] (*)
733cd21... Ada: Remove left-overs of front-end exception mechanism (*)
2cb1108... middle-end: Fix complex lowering of cabs with no LHS [PR120 (*)
6126909... libstdc++: Update LWG 4166 changes to concat_view::end() [P (*)
6b19e40... c++: uninitialized TARGET_EXPR and constexpr [PR120684] (*)
c612c50... libstdc++: Fix regression in std::uninitialized_fill for C+ (*)
8b7a779... Fortran: Fix out of bounds access in structure constructor' (*)
22b8806... ada: Fix alignment violation for mix of aligned and misalig (*)
aa622ab... ada: Fix wrong finalization of constrained subtype of uncon (*)
a30e425... ada: Fix missing error on too large Component_Size not mult (*)
81645c6... ada: Refine sanity check in Insert_Actions (*)
ce51aec... ada: Fix missing finalization with conditional expression i (*)
36b7726... ada: Fix crash with Finalizable in corner case (*)
181d761... ada: Fix crash with Finalizable in corner case (*)
c9c6392... ada: Fix assertion failure on finalizable aggregate (*)
4ea7021... ada: Fix wrong conversion of controlled array with represen (*)
2498cbb... Fixup dropping REG_EQUAL note in ext-dce (*)
8b3e6db... [committed][PR rtl-optimization/120550] Drop REG_EQUAL note (*)
698fefe... Daily bump. (*)
3b59959... Do not query further vector epilogues after a masked epilog (*)
977b8fb... i386: Change Diamond Rapids feature detect when model numbe (*)
9f44730... Daily bump. (*)
98bc42f... testsuite: Fix up gcc.target/powerpc/builtin_altivec_tr_stx (*)
79b82eb... Ada: Fix assertion failure for Finalizable aspect on tagged (*)
7fdf475... c++: Fix up cp_build_array_ref COND_EXPR handling [PR120471 (*)
fc36a90... libstdc++: Format %r, %x and %X using locale's time_put fac (*)
c3a639d... s390: Add -fno-stack-protector to 3 tests (*)
debd1cd... ada: Fix for compiler crash on function return with Relaxed (*)
177050b... ada: Compiler fails on unchecked deallocation for constrain (*)
25e6c44... ada: Small tweak to latest change (*)
5bd0302... ada: Fix wrong finalization of constrained subtype of uncon (*)
74cc201... ada: Dispatching call with mutably tagged objects (*)
484fb60... ada: Fix wrong finalization of constrained array derived fr (*)
54b5f78... ada: Small cleanup in the finalization machinery (*)
affc5eb... ada: Fix wrong finalization of temporary constrained array (*)
ce86985... tailc: Handle musttail in case of non-cleaned-up cleanups, (*)
497cb08... testsuite: Fix up pr119318.c test for big-endian [PR120082] (*)
a352fb3... Daily bump. (*)
9b7f1ec... ada: Make class-wide Max_Size_In_Storage_Elements return a (*)
411c1ee... ada: Fix bogus error for pragma No_Component_Reordering on (*)
29042b6... ada: Record type Put_Image procedures omitting discriminant (*)
cabca4d... ada: Fix crash on nested access-to-subprogram types (*)
36332b8... ada: Fix internal error on Ghost aspect applied to Big_Inte (*)
e94c683... ada: Fix internal error on expression function called for d (*)
53d2ca1... libstdc++: Report compilation error on formatting "%d" from (*)
4297261... Daily bump. (*)
ccaff41... Daily bump. (*)
06a26f4... Fix compilation of concatenation with illegal character con (*)
80c55b1... Ada: Fix assertion failure on problematic container aggrega (*)
c0a55fc... Daily bump. (*)
5808dd2... Fix misoptimization of CONSTRUCTOR with reverse SSO (*)
1b8a32a... Fortran: follow-up fix to checking of renamed-on-use interf (*)
e4c99f1... Daily bump. (*)
58323d4... Fortran: fix checking of renamed-on-use interface name [PR1 (*)
8d600e9... Bump LTO_minor_version (*)
59e5e86... tree-optimization/120729 - limit compile time in uninit_ana (*)
d8a9467... tree-optimization/120654 - ICE with range query from IVOPTs (*)
4a253f1... Daily bump. (*)
f48873c... [RISC-V] Fix ICE due to splitter emitting constant loads di (*)
8422524... Fortran: Source allocation of pure function result rejected (*)
cb3c5b7... aarch64: Incorrect removal of ZA restore [PR120624] (*)
2efe8cc... rtl-ssa: Reject non-address uses of autoinc regs [PR120347] (*)
9f817c9... i386: Remove CLDEMOTE for clients (*)
3260270... Daily bump. (*)
2e095cd... Daily bump. (*)
fa2e03e... tailc: Allow musttail tail calls with -fsanitize=address [P (*)
e5cf602... expand: Allow musttail tail calls with -fsanitize=address [ (*)
0be140d... Daily bump. (*)
2272b48... Daily bump. (*)
2c24509... Daily bump. (*)
bf284e8... [RISC-V][PR target/119971] Avoid losing shift count masking (*)
6583c3b... Daily bump. (*)
5e570c3... dfp: Further decimal_real_to_integer fixes [PR120631] (*)
b89ee9e... dfp, real: Fix up FLOAT_EXPR/FIX_TRUNC_EXPR constant foldin (*)
9540ef3... Daily bump. (*)
f34f1b1... Fortran: fix checking of MOLD= in ALLOCATE statements [PR51 (*)
5789351... doc: allow gcov.texi to be processed by makeinfo 4.13 (*)
bd02058... doc: allow extend.texi to be processed by makeinfo 4.13 (*)
416a7fe... Daily bump. (*)
f3dcc49... crc: Fix up ICE from optimize_crc_loop [PR120677] (*)
9803e23... Daily bump. (*)
2f0ccc3... Daily bump. (*)
0daf986... Daily bump. (*)
61789b5... AVR: Fix PR120423 / PR116389. (*)
6923d41... Daily bump. (*)
7821afa... Fix test case for PR117811 which failed for int < 32 bit. (*)
f45c7c4... recip: Reset range info when replacing sqrt with rsqrt [PR1 (*)
7bd9794... real: Fix up real_from_integer [PR120547] (*)
5a349dc... tree-chrec: Use signed_type_for in convert_affine_scev (*)
1549bb9... Fortran: Fix missing substring ref for allocatable saved va (*)
88ec0fe... Daily bump. (*)
e7041c8... Update gcc es.po (*)
bbe9ec9... libstdc++: Do not specialize std::formatter for incomplete (*)
f5fc1c6... ipa: When inlining, don't combine PT JFs changing signednes (*)
36bc863... ada: Fix documentation of Generalized Finalization extensio (*)
3a4d64e... ada: Fix wrong visibility over discriminants (*)
67c4948... ada: Tweak special handling of synchronized type scopes (*)
ea4155a... ada: Small tweak to latest change (*)
0bb1386... ada: Document supported GCC optimization switches (*)
98117e9... Daily bump. (*)
0ac2299... Daily bump. (*)
5327eef... libstdc++: Make system_clock::to_time_t always_inline [PR99 (*)
974d59a... libstdc++: Fix std::format thousands separators when sign p (*)
615a92a... vectorizer: Fix riscv build [PR120042] (*)
a35f642... ada: Error on subtype with static predicate used in case_ex (*)
e249cec... ada: Fix fallout of latest change (*)
d02a2fe... ada: Fix wrong initialization of library-level object by co (*)
4aca5bc... ada: Storage_Error on Ordered_Maps container aggregate with (*)
8a4b72a... ada: Fix infinite loop with aggregate in generic unit (*)
2859883... ada: Fix use-after-free in Compute_All_Tasks (*)
ba729e2... ext-dce: Don't refine live width with SUBREG mode if !TRULY (*)
62724ea... Daily bump. (*)
e4940c0... c++: recursive template with deduced return [PR120555] (*)
4e4684c... c++: constexpr prvalues vs genericize [PR120502] (*)
d96603a... ada: Support fixed-lower-bound array types as generic actua (*)
6cc5c01... ada: Reject component-related aspects on formal non-array t (*)
2fd267b... ada: Fix glitch in handling of Atomic_Components on generic (*)
f59c4d4... ada: Missing discriminant check on assignment of Bounded_Ve (*)
e68026c... ada: Check validity using signedness from the type and not (*)
8a63f6b... ada: Incorrect creation of corresponding expression of clas (*)
823e973... ada: Fix spurious error on anonymous array initialized by c (*)
c8934b1... Daily bump. (*)
4caedcd... Daily bump. (*)
69eb171... Daily bump. (*)
f59d33a... ada: Constant_Indexing used when context requires a variabl (*)
e0777e7... ada: Fix libgpr2 build failure with compiler built with ass (*)
cb3e765... ada: Fix wrong initialization of library-level object by co (*)
1189522... ada: Incorrect unresolved operator name in an instantiation (*)
855fe36... ada: Fix internal error on allocator involving interface ty (*)
649bde8... ada: Fix for validity checking of limited scalar types (*)
a69ab79... gcn: Update --with-arch= for newer archs (*)
e75e42f... libstdc++: Fix flat_map::operator[] for const lvalue keys [ (*)
b2338eb... libstdc++: Fix format call in formatting with empty specs f (*)
8cb0127... tree-optimization/120357 - ICE with early break vectorizati (*)
09884fa... tree-optimization/120341 - stores into STRING_CSTs can trap (*)
44792a6... rtl-optimization/120182 - wrong-code with RTL DSE and const (*)
ca8032d... Fix gcc.dg/tree-ssa/ssa-dom-thread-7.c for aarch64 (*)
4d375eb... tree-optimization/120003 - missed jump threading (*)
8fb3d90... tree-optimization/119960 - failed external SLP promotion (*)
7da2b6d... tree-optimization/116352 - amend previous fix (*)
05ef04d... tree-optimization/119960 - add validity checking to SLP sch (*)
6bb3169... tree-optimization/119960 - fix and guard get_later_stmt (*)
e93f028... Fix regression from x86 multi-epilogue tuning (*)
6346562... Daily bump. (*)
d056ac5... ada: Spurious compilation error with repeated loop index (*)
48a5910... ada: Exception-raising loop incorrectly eliminated (*)
257a8dc... ada: Fix crash on access to protected return (*)
6b1c8f4... ada: Tweak caching of streaming subprograms (*)
b7e10f8... ada: Implement built-in-place expansion of two-pass array a (*)
9f9476c... ada: Reject Valid_Value arguments originating from Standard (*)
a871b23... ada: Error about assignment to limited target on aggregate (*)
09b0aac... ada: Fix buffer overflow for function call returning discri (*)
5738c9b... ada: Fix compile-time failure due to duplicated attribute s (*)
29447fb... ada: Avoid calling Resolve with Stand.Any_Fixed as the expe (*)
a52223c... ada: Compiler crash on array aggregate association iteratin (*)
d9fb0b4... Fix crash with constant initializer caused by IPA (*)
ea8d197... Daily bump. (*)
c77dd2d... Fortran: ICE due to missing locus with data statement for c (*)
55a9203... Daily bump. (*)
e8a36b0... Fortran: parameter inquiries of constant complex arrays [PR (*)
819b641... Fortran: fix regression introduced by commit r16-914-g787a8 (*)
25e4642... Fortran: fix parsing of type parameter inquiries of substri (*)
1299fd3... Daily bump. (*)
c096341... c++: lambda this capture and requires [PR120123] (*)
fff23f4... fortran: Fix debug info for unsigned(kind=1) and unsigned(k (*)
21e0a74... Fortran: Fix handling of parsed format strings. (*)
4856aff... Fortran: Adjust handling of optional comma in FORMAT. (*)
9e73425... Daily bump. (*)
771fcb9... libstdc++: Compare keys and values separately in flat_map:: (*)
48d6f5d... libstdc++: Fix tuple/pair confusion with std::erase_if(flat (*)
512a41f... Daily bump. (*)
41dee7d... Fortran: Fix c_associated argument checks. (*)
d8e7a2d... Type mismatch for passed external function (*)
1d3b863... Daily bump. (*)
d67a38c... OpenMP: Fix ICE and other issues in C/C++ metadirective err (*)
b368dd5... OpenMP: Fix ICE in metadirective recovery after error [PR12 (*)
9fa1f93... testsuite: Add testcase for GCC 13 branch s390 bug [PR12048 (*)
f54d6c1... Daily bump. (*)
d79b3dc... aarch64: Enable newly implemented features for FUJITSU-MONA (*)
4276b38... Daily bump. (*)
c38760c... libgomp.fortran/metadirective-1.f90: Expect 'error:' for nv (*)
772dc28... Daily bump. (*)
c2b90bf... Fix IPA-SRA issue with reverse SSO on specific pattern (*)
9933a96... doc: Fix typo in description of nonstring attribute (*)
c204037... libstdc++: Fix PSTL test iterators (*)
ae1c59c... libstdc++: Fix vector(from_range_t, R&&) for exceptions [PR (*)
a0e365b... AVR: target/120442 - Support f7_fdim / fdiml in LibF7. (*)
5ef8bbc... AVR: target/120441 - Fix f7_exp for |x| ≥ 512. (*)
156cc1c... Daily bump. (*)
d390c7e... c-c++-common/gomp/{attrs-,}metadirective-3.c: Fix expected (*)
cf619d4... libgomp.c-c++-common/metadirective-1.c: Expect 'error:' for (*)
9c8e20a... OpenMP/C++: Avoid ICE for BIND_EXPR with empty BIND_EXPR_BL (*)
afa69f8... Daily bump. (*)
4ac1fb5... MicroBlaze does not support speculative execution (CVE-2017 (*)
65c2baf... Daily bump. (*)
18f937f... Daily bump. (*)
a8f62a9... c++/modules: Fix merge of TLS init functions [PR120363] (*)
2486d94... c++/modules: Fix stream-in of member using-decls [PR120414] (*)
fd2a11e... Daily bump. (*)
6fb3dd1... Fortran: default-initialization and functions returning der (*)
8c4b236... Daily bump. (*)
7e58022... Daily bump. (*)
6683c72... Fortran: fix passing of inquiry ref of complex array to TRA (*)
c1db46f... tree-sra: Do not create stores into const aggregates (PR111 (*)
76d16fb... ipa: Dump cgraph_node UID instead of order into ipa-clones (*)
911cfea... libstdc++: Fix incorrect links to archived SGI STL docs (*)
2d1244a... c++/modules: Fix ICE on merge of instantiation with partial (*)
3ba1b0a... c++/modules: Always mark tinfo vars as TREE_ADDRESSABLE [PR (*)
fedf81e... Daily bump. (*)
06a10db... libstdc++: Fix some Clang -Wsystem-headers warnings in <ran (*)
4bc5697... libstdc++: Fix std::format of chrono::local_days with {} [P (*)
beb0ffd... libstdc++: Fix dangling pointer in fs::path::operator+=(*th (*)
53680c1... libstdc++: Fix std::format_kind primary template for Clang (*)
57f73c3... OpenMP/Fortran: Fix allocatable-component mapping of derive (*)
ab9ca3a... OpenMP: Fix mapping of zero-sized arrays with non-literal s (*)
6f607c9... libgomp.{c,fortran}/interop-{hip,cuda}: Fix dg-run target s (*)
24edffe... libgomp.fortran/map-alloc-comp-9{,-usm}.f90: Add unified_sh (*)
e71170d... 'libgomp.c/interop-hsa.c': GCN offloading only (*)
6ae29e2... OpenMP: Restore lost Fortran testcase for 'omp allocate' (*)
c37fa5f... OpenMP, GCN: Add interop-hsa testcase (*)
e8b69ee... libgomp/testsuite: Fix hip_header_nvidia check, add workaro (*)
951d02d... libgomp: Add additional OpenMP interop runtime tests (*)
f251e27... OpenMP: Add libgomp.fortran/target-enter-data-8.f90 (*)
f53afae... Daily bump. (*)
848e7b1... Daily bump. (*)
dc21cae... Fortran: Fix ICE with use of c_associated. (*)
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