https://gcc.gnu.org/g:181cb2943d53862aa41eab49a042dff991a3d94f
commit r16-1713-g181cb2943d53862aa41eab49a042dff991a3d94f
Author: Paul-Antoine Arras <par...@baylibre.com>
Date: Wed Jun 25 16:42:00 2025 +0000
RISC-V: update prepare_ternary_operands to handle vector-scalar case
[PR120828]
This is a followup to 92e1893e0 "RISC-V: Add patterns for vector-scalar
multiply-(subtract-)accumulate" that caused an ICE in some cases where the
mult
operands were wrongly swapped.
This patch ensures that operands are not swapped in the vector-scalar case.
PR target/120828
gcc/ChangeLog:
* config/riscv/riscv-v.cc (prepare_ternary_operands): Handle the
vector-scalar case.
Diff:
---
gcc/config/riscv/riscv-v.cc | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 45dd9256d020..a3d704e81cc4 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4723,7 +4723,7 @@ prepare_ternary_operands (rtx *ops)
ops[4], ops[1], ops[6], ops[7], ops[9]));
ops[5] = ops[4] = ops[0];
}
- else
+ else if (VECTOR_MODE_P (GET_MODE (ops[2])))
{
/* Swap the multiplication ops if the fallback value is the
second of the two. */
@@ -4733,8 +4733,10 @@ prepare_ternary_operands (rtx *ops)
/* TODO: ??? Maybe we could support splitting FMA (a, 4, b)
into PLUS (ASHIFT (a, 2), b) according to uarchs. */
}
- gcc_assert (rtx_equal_p (ops[5], RVV_VUNDEF (mode))
- || rtx_equal_p (ops[5], ops[2]) || rtx_equal_p (ops[5], ops[4]));
+ gcc_assert (
+ rtx_equal_p (ops[5], RVV_VUNDEF (mode)) || rtx_equal_p (ops[5], ops[2])
+ || (!VECTOR_MODE_P (GET_MODE (ops[2])) && rtx_equal_p (ops[5], ops[3]))
+ || rtx_equal_p (ops[5], ops[4]));
}
/* Expand VEC_MASK_LEN_{LOAD_LANES,STORE_LANES}. */
