https://gcc.gnu.org/g:467fa6d257efdedf7b59168c759c97d3cb08c17d
commit r16-1685-g467fa6d257efdedf7b59168c759c97d3cb08c17d
Author: Shahab Vahedi <sha...@synopsys.com>
Date: Wed Jun 25 17:22:45 2025 +0300
ARC: Use intrinsics for __builtin_add_overflow*()
This patch covers signed and unsigned additions. The generated code
would be something along these lines:
signed:
add.f r0, r1, r2
b.v @label
unsigned:
add.f r0, r1, r2
b.c @label
gcc/
* config/arc/arc-modes.def (CC_V): New mode.
* config/arc/arc-protos.h (arc_gen_unlikely_cbranch): New
function declaration.
* config/arc/arc.cc (arc_gen_unlikely_cbranch): New
function.
(get_arc_condition_code): Handle new mode.
* config/arc/arc.md (addvsi3_v, addvsi4, addsi3_c, uaddvsi4): New
patterns.
* config/arc/predicates.md (proper_comparison_operator): Handel
the new V_mode.
(equality_comparison_operator): Likewise.
gcc/testsuite/
* gcc.target/arc/overflow-1.c: New file
Diff:
---
gcc/config/arc/arc-modes.def | 1 +
gcc/config/arc/arc-protos.h | 1 +
gcc/config/arc/arc.cc | 22 +++++++
gcc/config/arc/arc.md | 50 +++++++++++++++
gcc/config/arc/predicates.md | 9 ++-
gcc/testsuite/gcc.target/arc/overflow-1.c | 100 ++++++++++++++++++++++++++++++
6 files changed, 182 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def
index cab46d7ce9c6..7c7dff9146a5 100644
--- a/gcc/config/arc/arc-modes.def
+++ b/gcc/config/arc/arc-modes.def
@@ -24,6 +24,7 @@ along with GCC; see the file COPYING3. If not see
CC_MODE (CC_ZN);
CC_MODE (CC_Z);
+CC_MODE (CC_V);
CC_MODE (CC_C);
CC_MODE (CC_FP_GT);
CC_MODE (CC_FP_GE);
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index cd82aa1ef5e5..2db643cea08c 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -55,6 +55,7 @@ extern bool arc_check_mov_const (HOST_WIDE_INT );
extern bool arc_split_mov_const (rtx *);
extern bool arc_can_use_return_insn (void);
extern bool arc_split_move_p (rtx *);
+extern void arc_gen_unlikely_cbranch (enum rtx_code, machine_mode, rtx);
#endif /* RTX_CODE */
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index 78ba814d223a..40308263ff33 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -1436,6 +1436,13 @@ get_arc_condition_code (rtx comparison)
case GEU : return ARC_CC_NC;
default : gcc_unreachable ();
}
+ case E_CC_Vmode:
+ switch (GET_CODE (comparison))
+ {
+ case EQ : return ARC_CC_NV;
+ case NE : return ARC_CC_V;
+ default : gcc_unreachable ();
+ }
case E_CC_FP_GTmode:
if (TARGET_ARGONAUT_SET && TARGET_SPFP)
switch (GET_CODE (comparison))
@@ -11543,6 +11550,21 @@ arc_libm_function_max_error (unsigned cfn,
machine_mode mode,
return default_libm_function_max_error (cfn, mode, boundary_p);
}
+void
+arc_gen_unlikely_cbranch (enum rtx_code cmp, machine_mode cc_mode, rtx label)
+{
+ rtx cc_reg, x;
+
+ cc_reg = gen_rtx_REG (cc_mode, CC_REG);
+ label = gen_rtx_LABEL_REF (VOIDmode, label);
+
+ x = gen_rtx_fmt_ee (cmp, VOIDmode, cc_reg, const0_rtx);
+ x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label, pc_rtx);
+
+ emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
+}
+
+
#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
#define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 1344d9c68b02..c81a7f19d228 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -2734,6 +2734,56 @@ archs4x, archs4xd"
}
[(set_attr "length" "8")])
+(define_insn "addsi3_v"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r, r")
+ (plus:SI (match_operand:SI 1 "register_operand" "r,r,0, r")
+ (match_operand:SI 2 "nonmemory_operand" "r,L,I,C32")))
+ (set (reg:CC_V CC_REG)
+ (compare:CC_V (sign_extend:DI (plus:SI (match_dup 1)
+ (match_dup 2)))
+ (plus:DI (sign_extend:DI (match_dup 1))
+ (sign_extend:DI (match_dup 2)))))]
+ ""
+ "add.f\\t%0,%1,%2"
+ [(set_attr "cond" "set")
+ (set_attr "type" "compare")
+ (set_attr "length" "4,4,4,8")])
+
+(define_expand "addvsi4"
+ [(match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand")
+ (label_ref (match_operand 3 "" ""))]
+ ""
+ "emit_insn (gen_addsi3_v (operands[0], operands[1], operands[2]));
+ arc_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
+ DONE;")
+
+(define_insn "addsi3_c"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r, r")
+ (plus:SI (match_operand:SI 1 "register_operand" "r,r,0, r")
+ (match_operand:SI 2 "nonmemory_operand" "r,L,I,C32")))
+ (set (reg:CC_C CC_REG)
+ (compare:CC_C (plus:SI (match_dup 1)
+ (match_dup 2))
+ (match_dup 1)))]
+ ""
+ "add.f\\t%0,%1,%2"
+ [(set_attr "cond" "set")
+ (set_attr "type" "compare")
+ (set_attr "length" "4,4,4,8")])
+
+(define_expand "uaddvsi4"
+ [(match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand")
+ (label_ref (match_operand 3 "" ""))]
+ ""
+ "emit_insn (gen_addsi3_c (operands[0], operands[1], operands[2]));
+ arc_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]);
+ DONE;")
+
+
(define_insn "add_f"
[(set (reg:CC_C CC_REG)
(compare:CC_C
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 209cda908054..f506cee8baf7 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -419,6 +419,8 @@
return code == EQ || code == NE;
case E_CC_Cmode:
return code == LTU || code == GEU;
+ case E_CC_Vmode:
+ return code == EQ || code == NE;
case E_CC_FP_GTmode:
return code == GT || code == UNLE;
case E_CC_FP_GEmode:
@@ -451,7 +453,12 @@
})
(define_predicate "equality_comparison_operator"
- (match_code "eq, ne"))
+ (match_code "eq, ne")
+ {
+ machine_mode opmode = GET_MODE (XEXP (op, 0));
+ return opmode != CC_Vmode;
+ }
+)
(define_predicate "ge_lt_comparison_operator"
(match_code "ge, lt"))
diff --git a/gcc/testsuite/gcc.target/arc/overflow-1.c
b/gcc/testsuite/gcc.target/arc/overflow-1.c
new file mode 100644
index 000000000000..01b3e8ad0fab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/overflow-1.c
@@ -0,0 +1,100 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*
+ * add.f r0,r0,r1
+ * st_s r0,[r2]
+ * mov_s r0,1
+ * j_s.d [blink]
+ * mov.nv r0,0
+ */
+bool add_overflow (int32_t a, int32_t b, int32_t *res)
+{
+ return __builtin_add_overflow (a, b, res);
+}
+
+/*
+ * add.f r0,r0,-1234
+ * st_s r0,[r1]
+ * mov_s r0,1
+ * j_s.d [blink]
+ * mov.nv r0,0
+ */
+bool addi_overflow (int32_t a, int32_t *res)
+{
+ return __builtin_add_overflow (a, -1234, res);
+}
+
+/*
+ * add.f r0,r0,r1
+ * st_s r0,[r2]
+ * mov_s r0,1
+ * j_s.d [blink]
+ * mov.hs r0,0
+ */
+bool uadd_overflow (uint32_t a, uint32_t b, uint32_t *res)
+{
+ return __builtin_add_overflow (a, b, res);
+}
+
+/*
+ * add.f r2,r0, 4321
+ * seths r0,r0,-4321
+ * j_s.d [blink]
+ * st_s r2,[r1]
+ */
+bool uaddi_overflow (uint32_t a, uint32_t *res)
+{
+ return __builtin_add_overflow (a, 4321, res);
+}
+
+/*
+ * add.f r0,r0,r1
+ * mov_s r0,1
+ * j_s.d [blink]
+ * mov.nv r0,0
+ */
+bool add_overflow_p (int32_t a, int32_t b, int32_t res)
+{
+ return __builtin_add_overflow_p (a, b, res);
+}
+
+/*
+ * add.f r0,r0,-1000
+ * mov_s r0,1
+ * j_s.d [blink]
+ * mov.nv r0,0
+ */
+bool addi_overflow_p (int32_t a, int32_t res)
+{
+ return __builtin_add_overflow_p (a, -1000, res);
+}
+
+/*
+ * add.f 0,r0,r1
+ * mov_s r0,1
+ * j_s.d [blink]
+ * mov.hs r0,0
+ */
+bool uadd_overflow_p (uint32_t a, uint32_t b, uint32_t res)
+{
+ return __builtin_add_overflow_p (a, b, res);
+}
+
+/*
+ * j_s.d [blink]
+ * seths r0,r0,-2000
+ */
+bool uaddi_overflow_p (uint32_t a, uint32_t res)
+{
+ return __builtin_add_overflow_p (a, 2000, res);
+}
+
+/* { dg-final { scan-assembler-times "add.f\\s\+" 7 } } */
+/* { dg-final { scan-assembler-times "mov\.nv\\s\+" 4 } } */
+/* { dg-final { scan-assembler-times "mov\.hs\\s\+" 2 } } */
+/* { dg-final { scan-assembler-times "seths\\s\+" 2 } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
