https://gcc.gnu.org/g:bf7162b321128ba93521a824e5a7a00d1cc3d1f8
commit r16-1639-gbf7162b321128ba93521a824e5a7a00d1cc3d1f8
Author: Jeff Law <j...@ventanamicro.com>
Date: Mon Jun 23 18:27:49 2025 -0600
[RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V
Fix typo in comment spotted by Peter B.
PR target/118241
gcc/
* config/riscv/predicates.md: Fix comment typo in recent change.
Diff:
---
gcc/config/riscv/predicates.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 8072d67fbd97..061904b6e000 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -27,7 +27,7 @@
(ior (match_operand 0 "const_arith_operand")
(match_operand 0 "register_operand")))
-;; REG or REG+D where D fits in a simm12 and has the low 4 bits
+;; REG or REG+D where D fits in a simm12 and has the low 5 bits
;; off. The REG+D form can be reloaded into a temporary if needed
;; after FP elimination if that exposes an invalid offset.
(define_predicate "prefetch_operand"
