https://gcc.gnu.org/g:a22ed5658797cc9ca4421e69db5d6259389a4156
commit r16-1541-ga22ed5658797cc9ca4421e69db5d6259389a4156
Author: Umesh Kalappa <ukalappa.m...@gmail.com>
Date: Tue Jun 17 07:23:41 2025 -0600
[PATCH v1] RISC-V: Use scratch reg for loop control
By using the scratch register for loop control rather than the output
of the lr instruction we can avoid an unnecessary "mv" instruction.
--
V2: Testcase update with no regressions found for the following the changes.
gcc/ChangeLog:
* config/riscv/sync.md (lrsc_atomic_exchange<mode>): Use scratch
register for loop control rather than lr output.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zalrsc.c: New test.
Diff:
---
gcc/config/riscv/sync.md | 11 +++++------
gcc/testsuite/gcc.target/riscv/zalrsc.c | 14 ++++++++++++++
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 726800a96623..a75ea6834e46 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -405,18 +405,17 @@
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_EXCHANGE))
(set (match_dup 1)
- (match_operand:GPR 2 "register_operand" "0"))
+ (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1
"!TARGET_ZAAMO && TARGET_ZALRSC"
{
return "1:\;"
- "lr.<amo>%I3\t%4, %1\;"
- "sc.<amo>%J3\t%0, %0, %1\;"
- "bnez\t%0, 1b\;"
- "mv\t%0, %4";
+ "lr.<amo>%I3\t%0, %1\;"
+ "sc.<amo>%J3\t%4, %z2, %1\;"
+ "bnez\t%4, 1b\";
}
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 16))])
+ (set (attr "length") (const_int 12))])
(define_expand "atomic_exchange<mode>"
[(match_operand:SHORT 0 "register_operand") ;; old value at mem
diff --git a/gcc/testsuite/gcc.target/riscv/zalrsc.c
b/gcc/testsuite/gcc.target/riscv/zalrsc.c
new file mode 100644
index 000000000000..19a26bfb47ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zalrsc.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imfd_zalrsc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } {"-O0"} } */
+
+/* lr.w/sc.w */
+int *i;
+int lr_sc(int v)
+{
+ return __atomic_exchange_4(i, v, __ATOMIC_RELAXED);
+}
+
+/* { dg-final { scan-assembler-times {\mlr.w} 1 } } */
+/* { dg-final { scan-assembler-times {\msc.w} 1 } } */
+/* { dg-final { scan-assembler-not {"mv\t"} } } */
