https://gcc.gnu.org/g:0dfbbfadd4b128ca440e3b38c0abbb0a6f1bf35e

commit 0dfbbfadd4b128ca440e3b38c0abbb0a6f1bf35e
Author: Michael Meissner <meiss...@linux.ibm.com>
Date:   Tue Jun 10 16:58:06 2025 -0400

    PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations
    
    2025-06-10  Michael Meissner  <meiss...@linux.ibm.com>
    
    gcc/
    
            PR target/117251
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to
            generate vector or => xor fusion if XXEVAL is supported.

Diff:
---
 gcc/config/rs6000/fusion.md    | 15 +++++++++------
 gcc/config/rs6000/genfusion.pl |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 032c87ac5765..d1f6a38b618a 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -3029,20 +3029,23 @@
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vor -> vxor
 (define_insn "*fuse_vor_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
-        (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" 
"v,v,v,v")
-                          (match_operand:VM 1 "altivec_register_operand" 
"v,v,v,v"))
-                 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
-   (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+  [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+        (xor:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" 
"v,v,v,wa,v")
+                          (match_operand:VM 1 "vector_fusion_operand" 
"v,v,v,wa,v"))
+                 (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
+   (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
   "(TARGET_P10_FUSION)"
   "@
    vor %3,%1,%0\;vxor %3,%3,%2
    vor %3,%1,%0\;vxor %3,%3,%2
    vor %3,%1,%0\;vxor %3,%3,%2
+   xxeval %x3,%x2,%x1,%x0,120
    vor %4,%1,%0\;vxor %3,%4,%2"
   [(set_attr "type" "fused_vector")
    (set_attr "cost" "6")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "prefixed" "*,*,*,yes,*")
+   (set_attr "isa" "*,*,*,xxeval,*")])
 
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vorc -> vxor
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 6af4c5d7a182..97681f37d0fa 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -236,6 +236,7 @@ sub gen_logical_addsubf
       "vxor_vxor"   => 105,
       "vxor_vor"    => 111,
       "vnor_vnor"   => 112,
+      "vor_vxor"    => 120,
     );
 
     KIND: foreach $kind ('scalar','vector') {

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