https://gcc.gnu.org/g:daee1935f4e366c09fc085905cb49bbf264c5663
commit r16-1296-gdaee1935f4e366c09fc085905cb49bbf264c5663
Author: Pan Li <pan2...@intel.com>
Date: Sun Jun 8 16:53:05 2025 +0800
RISC-V: Add test for vec_duplicate + vrem.vv combine case 0 with GR2VR cost
0, 2 and 15
Add asm dump check test for vec_duplicate + vrem.vv combine to vrem.vx,
with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
for vrem.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c | 15 ++
.../riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c | 15 ++
.../riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c | 15 ++
.../riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c | 15 ++
17 files changed, 280 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index d88e76b5d99c..893d910538ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 53189c21d041..26170de40d0c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 5059beb4c6de..04d1fcb5f81f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 4bbe5a40ee0e..89d37af3114e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 0437db48f59f..b9f8bd9365a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-not {vxor.vx} } } */
/* { dg-final { scan-assembler-not {vmul.vx} } } */
/* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 95ed403e1eef..d2be881904ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-not {vxor.vx} } } */
/* { dg-final { scan-assembler-not {vmul.vx} } } */
/* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index f8912a0bac6c..d1b85ee04fb9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-not {vxor.vx} } } */
/* { dg-final { scan-assembler-not {vmul.vx} } } */
/* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 3c8f9154a247..30a39282081c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-not {vxor.vx} } } */
/* { dg-final { scan-assembler-not {vmul.vx} } } */
/* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index f49dae498bf2..5210c0da3632 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-not {vxor.vx} } } */
/* { dg-final { scan-assembler-not {vmul.vx} } } */
/* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 8f502a31c6cc..5b0db088e62f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-not {vxor.vx} } } */
/* { dg-final { scan-assembler-not {vmul.vx} } } */
/* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 3277bf24453a..8d528d8b7c90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-not {vxor.vx} } } */
/* { dg-final { scan-assembler-not {vmul.vx} } } */
/* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 25ed2ad18ce8..85e79ac1d6b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
/* { dg-final { scan-assembler-not {vxor.vx} } } */
/* { dg-final { scan-assembler-not {vmul.vx} } } */
/* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 5130709050dd..82391fc25680 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -2946,4 +2946,200 @@ uint64_t TEST_BINARY_DATA(uint64_t, div)[][3][N] =
},
};
+int8_t TEST_BINARY_DATA(int8_t, rem)[][3][N] =
+{
+ {
+ { 2 },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { 127 },
+ {
+ 127, 127, 127, 127,
+ -1, -1, -1, -1,
+ -128, -128, -128, -128,
+ -2, -2, -2, -2,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { -128 },
+ {
+ -128, -128, -128, -128,
+ 1, 1, 1, 1,
+ 127, 127, 127, 127,
+ 2, 2, 2, 2,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 127, 127, 127, 127,
+ 2, 2, 2, 2,
+ },
+ },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, rem)[][3][N] =
+{
+ {
+ { 2 },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { 32767 },
+ {
+ 32767, 32767, 32767, 32767,
+ -1, -1, -1, -1,
+ -32768, -32768, -32768, -32768,
+ -2, -2, -2, -2,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { -32768 },
+ {
+ -32768, -32768, -32768, -32768,
+ 1, 1, 1, 1,
+ 32767, 32767, 32767, 32767,
+ 2, 2, 2, 2,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 32767, 32767, 32767, 32767,
+ 2, 2, 2, 2,
+ },
+ },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, rem)[][3][N] =
+{
+ {
+ { 2 },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { 2147483647 },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ -1, -1, -1, -1,
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ -2, -2, -2, -2,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { -2147483648 },
+ {
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ 1, 1, 1, 1,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2, 2, 2, 2,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2, 2, 2, 2,
+ },
+ },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, rem)[][3][N] =
+{
+ {
+ { 2 },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { 9223372036854775807ll },
+ {
+ 9223372036854775807ll, 9223372036854775807ll,
9223372036854775807ll, 9223372036854775807ll,
+ -1, -1,
-1, -1,
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ -2, -2,
-2, -2,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { -9223372036854775808ull },
+ {
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ 1, 1,
1, 1,
+ 9223372036854775807ll, 9223372036854775807ll,
9223372036854775807ll, 9223372036854775807ll,
+ 2, 2,
2, 2,
+ },
+ {
+ 0, 0, 0,
0,
+ 1, 1, 1,
1,
+ 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll,
9223372036854775807ll,
+ 2, 2, 2,
2,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c
new file mode 100644
index 000000000000..4320789a57a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int16_t
+#define NAME rem
+
+DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c
new file mode 100644
index 000000000000..43a001b41910
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+#define NAME rem
+
+DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c
new file mode 100644
index 000000000000..2e9b43af0fa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int64_t
+#define NAME rem
+
+DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c
new file mode 100644
index 000000000000..d4185c74417c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int8_t
+#define NAME rem
+
+DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
