[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Add svbare extension.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:bed8b673f96ad1225dd33578c744dfc1b2a8a2a7

commit bed8b673f96ad1225dd33578c744dfc1b2a8a2a7
Author: Dongyan Chen <chendong...@isrc.iscas.ac.cn>
Date:   Wed Jun 4 07:57:01 2025 -0600

    [PATCH v2] RISC-V: Add svbare extension.
    
    This patch support svbare extension, which is an extension in RVA23 profile.
    To enable GCC to recognize and process svbare extension correctly at 
compile time.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-ext.def: New extension defs.
            * config/riscv/riscv-ext.opt: Ditto.
            * doc/riscv-ext.texi: Ditto.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/arch-60.c: New test.
    
    (cherry picked from commit 07e3ed74a2b648c0ce8e823bbf5bd8f23383efa1)

Diff:
---
 gcc/config/riscv/riscv-ext.def           | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt           |  2 ++
 gcc/doc/riscv-ext.texi                   |  4 ++++
 gcc/testsuite/gcc.target/riscv/arch-60.c |  5 +++++
 4 files changed, 24 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 2d052c152068..c3d0bd42b200 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1961,6 +1961,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ svbare,
+  /* UPPERCAE_NAME */ SVBARE,
+  /* FULL_NAME */ "Satp mode bare is supported",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 #include "riscv-ext-corev.def"
 #include "riscv-ext-sifive.def"
 #include "riscv-ext-thead.def"
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index e0314430ffb1..3e5cbb34898e 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -379,6 +379,8 @@ Mask(SVADU) Var(riscv_sv_subext)
 
 Mask(SVADE) Var(riscv_sv_subext)
 
+Mask(SVBARE) Var(riscv_sv_subext)
+
 Mask(XCVALU) Var(riscv_xcv_subext)
 
 Mask(XCVBI) Var(riscv_xcv_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index e7e1f75cca6d..3e6541ac732b 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -582,6 +582,10 @@
 @tab 1.0
 @tab Cause exception when hardware updating of A/D bits is disabled
 
+@item svbare
+@tab 1.0
+@tab Satp mode bare is supported
+
 @item xcvalu
 @tab 1.0
 @tab Core-V miscellaneous ALU extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-60.c 
b/gcc/testsuite/gcc.target/riscv/arch-60.c
new file mode 100644
index 000000000000..ea599f20522d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-60.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_svbare -mabi=lp64" } */
+int foo()
+{
+}