https://gcc.gnu.org/g:a16aae22d395fa90f59a781b2911e40793c36b88
commit a16aae22d395fa90f59a781b2911e40793c36b88
Author: Pan Li <pan2...@intel.com>
Date: Mon Jun 2 16:56:59 2025 +0800
RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost
This patch would like to combine the vec_duplicate + vdiv.vv to the
vdiv.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have example code like below, GR2VR cost is 0.
#define DEF_VX_BINARY(T, OP) \
void \
test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
{ \
for (unsigned i = 0; i < n; i++) \
out[i] = in[i] OP x; \
}
DEF_VX_BINARY(int32_t, /)
Before this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ vsetvli a5,zero,e32,m1,ta,ma
13 │ vmv.v.x v2,a2
14 │ slli a3,a3,32
15 │ srli a3,a3,32
16 │ .L3:
17 │ vsetvli a5,a3,e32,m1,ta,ma
18 │ vle32.v v1,0(a1)
19 │ slli a4,a5,2
20 │ sub a3,a3,a5
21 │ add a1,a1,a4
22 │ vdiv.vv v1,v1,v2
23 │ vse32.v v1,0(a0)
24 │ add a0,a0,a4
25 │ bne a3,zero,.L3
After this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ slli a3,a3,32
13 │ srli a3,a3,32
14 │ .L3:
15 │ vsetvli a5,a3,e32,m1,ta,ma
16 │ vle32.v v1,0(a1)
17 │ slli a4,a5,2
18 │ sub a3,a3,a5
19 │ add a1,a1,a4
20 │ vdiv.vx v1,v1,a2
21 │ vse32.v v1,0(a0)
22 │ add a0,a0,a4
23 │ bne a3,zero,.L3
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vx_binary_vec_vec_dup): Add new
case for DIV op.
* config/riscv/riscv.cc (get_vector_binary_rtx_cost): Add new func
to get the cost of vector binary.
(riscv_rtx_costs): Add div rtx match and leverage above wrap to
get cost.
* config/riscv/vector-iterators.md: Add new op div to
no_shift_vx_op.
Signed-off-by: Pan Li <pan2...@intel.com>
(cherry picked from commit 451737734b8913c5de8cfe597d5d20477af6c5ef)
Diff:
---
gcc/config/riscv/riscv-v.cc | 1 +
gcc/config/riscv/riscv.cc | 34 ++++++++++++++++++++++++++++++++++
gcc/config/riscv/vector-iterators.md | 2 +-
3 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 616279757250..a41317f322f7 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5567,6 +5567,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx
op_2,
case IOR:
case XOR:
case MULT:
+ case DIV:
icode = code_for_pred_scalar (code, mode);
break;
default:
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 06a8b5175c2b..b168a6414988 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3891,6 +3891,25 @@ riscv_extend_cost (rtx op, bool unsigned_p)
return COSTS_N_INSNS (2);
}
+/* Return the cost of the vector binary rtx like add, minus, mult.
+ The cost of gr2vr will be appended if there one of the op comes
+ from the VEC_DUPLICATE. */
+
+static int
+get_vector_binary_rtx_cost (rtx x, int gr2vr_cost)
+{
+ gcc_assert (riscv_v_ext_mode_p (GET_MODE (x)));
+
+ rtx op_0 = XEXP (x, 0);
+ rtx op_1 = XEXP (x, 1);
+
+ if (GET_CODE (op_0) == VEC_DUPLICATE
+ || GET_CODE (op_1) == VEC_DUPLICATE)
+ return (gr2vr_cost + 1) * COSTS_N_INSNS (1);
+ else
+ return COSTS_N_INSNS (1);
+}
+
/* Implement TARGET_RTX_COSTS. */
#define SINGLE_SHIFT_COST 1
@@ -3915,6 +3934,21 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
case VEC_DUPLICATE:
*total = gr2vr_cost * COSTS_N_INSNS (1);
break;
+ case IF_THEN_ELSE:
+ {
+ rtx op_1 = XEXP (x, 1);
+
+ switch (GET_CODE (op_1))
+ {
+ case DIV:
+ *total = get_vector_binary_rtx_cost (op_1, gr2vr_cost);
+ break;
+ default:
+ *total = COSTS_N_INSNS (1);
+ break;
+ }
+ }
+ break;
case PLUS:
case MINUS:
case AND:
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 2bd99ee5372b..62fd1c09400b 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,7 +4042,7 @@
])
(define_code_iterator any_int_binop_no_shift_vx [
- plus minus and ior xor mult
+ plus minus and ior xor mult div
])
(define_code_iterator any_int_unop [neg not])
