https://gcc.gnu.org/g:28106a0c5d18173832d8013dccbb6fcc71646868
commit r16-1105-g28106a0c5d18173832d8013dccbb6fcc71646868
Author: Dongyan Chen <chendong...@isrc.iscas.ac.cn>
Date: Wed Jun 4 08:03:31 2025 -0600
[PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
This patch implies zicsr for svade and svadu extensions.
According to the riscv-privileged spec, the svade and svadu extensions
are privileged instructions, so they should imply zicsr.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: Imply zicsr.
Diff:
---
gcc/config/riscv/riscv-ext.def | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index c3d0bd42b200..0e989e122195 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1941,7 +1941,7 @@ DEFINE_RISCV_EXT(
/* FULL_NAME */ "Hardware Updating of A/D Bits extension",
/* DESC */ "",
/* URL */ ,
- /* DEP_EXTS */ ({}),
+ /* DEP_EXTS */ ({"zicsr"}),
/* SUPPORTED_VERSIONS */ ({{1, 0}}),
/* FLAG_GROUP */ sv,
/* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
@@ -1954,7 +1954,7 @@ DEFINE_RISCV_EXT(
/* FULL_NAME */ "Cause exception when hardware updating of A/D bits is
disabled",
/* DESC */ "",
/* URL */ ,
- /* DEP_EXTS */ ({}),
+ /* DEP_EXTS */ ({"zicsr"}),
/* SUPPORTED_VERSIONS */ ({{1, 0}}),
/* FLAG_GROUP */ sv,
/* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
