https://gcc.gnu.org/g:5b665add60b8b6e07a7a90d906a7e64ad7e46e6d
commit 5b665add60b8b6e07a7a90d906a7e64ad7e46e6d
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Jun 3 19:10:25 2025 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.bugs | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 7341470f50dc..a2ba00af3a38 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,33 @@
+==================== Branch work210-bugs, patch #110 ====================
+
+PR target/108958 -- simplify mtvsrdd to zero extend GPR DImode to VSX TImode
+
+Previously GCC would zero extend a DImode GPR value to TImode by first zero
+extending the DImode value into a GPR TImode register pair, and then do a
+MTVSRDD to move this value to a VSX register.
+
+This patch creates a peephole2 to catch this case, and it eliminates creating
+the TImode variable. Instead it just does the MTVSRDD instruction directly.
+
+I have built GCC with the patches in this patch set applied on both little and
+big endian PowerPC systems and there were no regressions. Can I apply this
+patch to GCC 16?
+
+2025-06-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ PR target/108958
+ * config/rs6000/rs6000.md (UNSPEC_ZERO_EXTEND): New unspec.
+ (zero_extendsiti2 peephole2): Add a peephole2 to simplify zero extend
+ between DImode value in a GPR to a TImode target in a vector register.
+ (zero_extendsiti2_vsx): New insn.
+
+gcc/testsuite/
+
+ PR target/108958
+ * gcc.target/powerpc/pr108958.c: New test.
+
==================== Branch work210-bugs, patch #100 ====================
Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.
