https://gcc.gnu.org/g:6ccf845d9fa157e7ebcf2c589a9fc5d8f298961f
commit r16-936-g6ccf845d9fa157e7ebcf2c589a9fc5d8f298961f
Author: Robin Dapp <rd...@ventanamicro.com>
Date: Mon May 26 16:16:36 2025 +0200
RISC-V: Avoid division by zero in check_builtin_call [PR120436].
In check_builtin_call we eventually perform a division by zero when no
vector modes are present. This patch just avoids the division in that
case.
PR target/120436
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct vset_def):
Avoid division by zero.
(struct vget_def): Ditto.
* config/riscv/riscv-vector-builtins.h (struct function_group_info):
Use required_extensions_specified instead of duplicating code.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr120436.c: New test.
Diff:
---
gcc/config/riscv/riscv-vector-builtins-shapes.cc | 4 +++
gcc/config/riscv/riscv-vector-builtins.h | 40 +---------------------
gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c | 16 +++++++++
3 files changed, 21 insertions(+), 39 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index b855d4c5fa5a..9832eb9e3d1b 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -908,6 +908,8 @@ struct vset_def : public build_base
{
poly_int64 outer_size = GET_MODE_SIZE (c.arg_mode (0));
poly_int64 inner_size = GET_MODE_SIZE (c.arg_mode (2));
+ if (maybe_eq (inner_size, 0))
+ return false;
unsigned int nvecs = exact_div (outer_size, inner_size).to_constant ();
return c.require_immediate (1, 0, nvecs - 1);
}
@@ -920,6 +922,8 @@ struct vget_def : public misc_def
{
poly_int64 outer_size = GET_MODE_SIZE (c.arg_mode (0));
poly_int64 inner_size = GET_MODE_SIZE (c.ret_mode ());
+ if (maybe_eq (inner_size, 0))
+ return false;
unsigned int nvecs = exact_div (outer_size, inner_size).to_constant ();
return c.require_immediate (1, 0, nvecs - 1);
}
diff --git a/gcc/config/riscv/riscv-vector-builtins.h
b/gcc/config/riscv/riscv-vector-builtins.h
index ffc289364b06..1f2587ab6afa 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -331,45 +331,7 @@ struct function_group_info
/* Return true if required extension is enabled */
bool match (required_ext ext_value) const
{
- switch (ext_value)
- {
- case VECTOR_EXT:
- return TARGET_VECTOR;
- case ZVBB_EXT:
- return TARGET_ZVBB;
- case ZVBB_OR_ZVKB_EXT:
- return (TARGET_ZVBB || TARGET_ZVKB);
- case ZVBC_EXT:
- return TARGET_ZVBC;
- case ZVKG_EXT:
- return TARGET_ZVKG;
- case ZVKNED_EXT:
- return TARGET_ZVKNED;
- case ZVKNHA_OR_ZVKNHB_EXT:
- return (TARGET_ZVKNHA || TARGET_ZVKNHB);
- case ZVKNHB_EXT:
- return TARGET_ZVKNHB;
- case ZVKSED_EXT:
- return TARGET_ZVKSED;
- case ZVKSH_EXT:
- return TARGET_ZVKSH;
- case XTHEADVECTOR_EXT:
- return TARGET_XTHEADVECTOR;
- case ZVFBFMIN_EXT:
- return TARGET_ZVFBFMIN;
- case ZVFBFWMA_EXT:
- return TARGET_ZVFBFWMA;
- case XSFVQMACCQOQ_EXT:
- return TARGET_XSFVQMACCQOQ;
- case XSFVQMACCDOD_EXT:
- return TARGET_XSFVQMACCDOD;
- case XSFVFNRCLIPXFQF_EXT:
- return TARGET_XSFVFNRCLIPXFQF;
- case XSFVCP_EXT:
- return TARGET_XSFVCP;
- default:
- gcc_unreachable ();
- }
+ return required_extensions_specified (ext_value);
}
/* The base name, as a string. */
const char *base_name;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c
new file mode 100644
index 000000000000..d22091e59490
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O0" } */
+
+/* Use -O0 as otherwise the unused intrinsics get
+ optimized away. We used to ICE here instead of
+ emitting an error. */
+
+#include "riscv_vector.h"
+
+void
+clean_subreg (int32_t *in, int32_t *out, size_t m) /* { dg-error {this
operation requires the RVV ISA extension} } */
+{
+ vint16m8_t v24, v8, v16;
+ vint32m8_t result = __riscv_vle32_v_i32m8 (in, 32); /* { dg-error {built-in
function '__riscv_vle32_v_i32m8\(in, 32\)' requires the 'v' ISA extension} } */
+ vint32m1_t v0 = __riscv_vget_v_i32m8_i32m1 (result, 0);
+}
