https://gcc.gnu.org/g:d64108265568594f7f175f5cef574216e686918e
commit d64108265568594f7f175f5cef574216e686918e
Author: Pan Li <pan2...@intel.com>
Date: Mon May 19 10:06:35 2025 +0800
RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC]
Tweak the asm check with define T uint8_t for adding more
vx test easily, as well as less possibility to make mistake.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Extract
define T as type for testing.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
(cherry picked from commit dd8ee1df28e0a26b666d64a6098a121fd22aa90d)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 9 +++++----
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c | 8 +++++---
48 files changed, 240 insertions(+), 145 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 015b08666683..47fa654e62d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int16_t, +, add)
-DEF_VX_BINARY_CASE_0(int16_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int16_t, -, rsub);
+#define T int16_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index f0a88e8da87a..9e16eaf59304 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int32_t, +, add)
-DEF_VX_BINARY_CASE_0(int32_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int32_t, -, rsub);
+#define T int32_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index fbf9f6a930fb..52271bee7710 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int64_t, +, add)
-DEF_VX_BINARY_CASE_0(int64_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int64_t, -, rsub);
+#define T int64_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 55309308573e..ac822fb66c8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int8_t, +, add)
-DEF_VX_BINARY_CASE_0(int8_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int8_t, -, rsub);
+#define T int8_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 15edd71a438e..f4e46b7e973e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint16_t, +, add)
-DEF_VX_BINARY_CASE_0(uint16_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint16_t, -, rsub);
+#define T uint16_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 992083e72353..9b83b6616192 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint32_t, +, add)
-DEF_VX_BINARY_CASE_0(uint32_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint32_t, -, rsub);
+#define T uint32_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index bb445f6e0ffd..be807889d729 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint64_t, +, add)
-DEF_VX_BINARY_CASE_0(uint64_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint64_t, -, rsub);
+#define T uint64_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 73e144b06eee..5928c3f3f286 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint8_t, +, add)
-DEF_VX_BINARY_CASE_0(uint8_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint8_t, -, rsub);
+#define T uint8_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index c55eaaac278a..631f035d2e57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int16_t, +, add)
-DEF_VX_BINARY_CASE_0(int16_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int16_t, -, rsub);
+#define T int16_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 0a0258ccfee3..bbef0a23ccc3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int32_t, +, add)
-DEF_VX_BINARY_CASE_0(int32_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int32_t, -, rsub);
+#define T int32_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 4956315ee146..f4999fe899e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int64_t, +, add)
-DEF_VX_BINARY_CASE_0(int64_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int64_t, -, rsub);
+#define T int64_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index c1fa3b605d7c..3ddfda0cfdbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int8_t, +, add)
-DEF_VX_BINARY_CASE_0(int8_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int8_t, -, rsub);
+#define T int8_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 5dca3850240f..a4e2eb843581 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint16_t, +, add)
-DEF_VX_BINARY_CASE_0(uint16_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint16_t, -, rsub);
+#define T uint16_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 4460fc06d00a..87ea54d0d023 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint32_t, +, add)
-DEF_VX_BINARY_CASE_0(uint32_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint32_t, -, rsub);
+#define T uint32_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index e8282c3d2198..990145ccc3c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint64_t, +, add)
-DEF_VX_BINARY_CASE_0(uint64_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int64_t, -, rsub);
+#define T uint64_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 7b744f1b460f..d1495a4c4867 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint8_t, +, add)
-DEF_VX_BINARY_CASE_0(uint8_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint8_t, -, rsub);
+#define T uint8_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index b5f36ff3a443..9c3102a24c04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int16_t, +, add)
-DEF_VX_BINARY_CASE_0(int16_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int16_t, -, rsub);
+#define T int16_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 93ba98d57e9c..7da01011ce75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int32_t, +, add)
-DEF_VX_BINARY_CASE_0(int32_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int32_t, -, rsub);
+#define T int32_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index e73fbce01067..7e77db986bfd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int64_t, +, add)
-DEF_VX_BINARY_CASE_0(int64_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int64_t, -, rsub);
+#define T int64_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 2a3a6f1884ba..957654fa1fe7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(int8_t, +, add)
-DEF_VX_BINARY_CASE_0(int8_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(int8_t, -, rsub);
+#define T int8_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 63358cd3354b..a62334adb4d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint16_t, +, add)
-DEF_VX_BINARY_CASE_0(uint16_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint16_t, -, rsub);
+#define T uint16_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 6ed098773c70..d7b31e2b589e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint32_t, +, add)
-DEF_VX_BINARY_CASE_0(uint32_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint32_t, -, rsub);
+#define T uint32_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index f2bfe28f1a7d..22f555082797 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint64_t, +, add)
-DEF_VX_BINARY_CASE_0(uint64_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint64_t, -, rsub);
+#define T uint64_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index a89d4a002680..3473c5ffc6c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_0(uint8_t, +, add)
-DEF_VX_BINARY_CASE_0(uint8_t, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(uint8_t, -, rsub);
+#define T uint8_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
+DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
index 4d1085693133..6f59b07d236c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
+#define T int16_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
index 410d9ffcfeaa..69b2227d889a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
+#define T int32_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
index 51b207055bd6..8ea88d4d75b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
-DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
-DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
+#define T int64_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
index ff7773daee34..ec937d6458e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
+#define T int8_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
index 00110752964b..9d04f40ac906 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
+#define T uint16_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
index ecd405a35742..af01bf5f82aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_CASE_1(uint32_t, -, sub, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_REVERSE_CASE_1(uint32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
+#define T uint32_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
index b712addf689e..b83b31ddab9d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint64_t, +, add, VX_BINARY_BODY)
-DEF_VX_BINARY_CASE_1(uint64_t, -, sub, VX_BINARY_BODY)
-DEF_VX_BINARY_REVERSE_CASE_1(uint64_t, -, rsub, VX_BINARY_REVERSE_BODY);
+#define T uint64_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c
index 9c9f37d50c5b..dc7be4ca8e01 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint8_t, +, add, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_CASE_1(uint8_t, -, sub, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_REVERSE_CASE_1(uint8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
+#define T uint8_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
index 3f33c45fafb2..ebdae502298f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
+#define T int16_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
index 059cf0b1d2e0..fadc0ce9dee6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
+#define T int32_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
index 9ac1dd067147..c3529e98ab66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
-DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
-DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
+#define T int64_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
index 63d0a820aa93..d196eb889b1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
+#define T int8_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c
index fe0ab0ea0818..623a718f140f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
+#define T uint16_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
index 305f3564bb5c..95cc0ff6e975 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_CASE_1(uint32_t, -, sub, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_REVERSE_CASE_1(uint32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
+#define T uint32_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c
index bb95764f914b..16b7c9bb88d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint64_t, +, add, VX_BINARY_BODY)
-DEF_VX_BINARY_CASE_1(uint64_t, -, sub, VX_BINARY_BODY)
-DEF_VX_BINARY_REVERSE_CASE_1(uint64_t, -, rsub, VX_BINARY_REVERSE_BODY);
+#define T uint64_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c
index 347752af9613..438eaec34945 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint8_t, +, add, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_CASE_1(uint8_t, -, sub, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_REVERSE_CASE_1(uint8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
+#define T uint8_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index ce1b40fd1740..65104e138209 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
+#define T int16_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index 7326ded06f0e..631b62f113ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
+#define T int32_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 7b8b63dd3cef..64ea74169303 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
-DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
-DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
+#define T int64_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index f440b7075dc2..2b26ce4f6a0c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
+#define T int8_t
+
+DEF_VX_BINARY_CASE_1(T, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1(T, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(T, -, rsub, VX_BINARY_REVERSE_BODY_X16);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index c36c5cb64165..195118676169 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -1,12 +1,13 @@
-
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
+#define T uint16_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c
index cfbcd9e57720..28508d6d7c70 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_CASE_1(uint32_t, -, sub, VX_BINARY_BODY_X4)
-DEF_VX_BINARY_REVERSE_CASE_1(uint32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
+#define T uint32_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c
index 5d837f1a6d47..fa50d0f3b134 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint64_t, +, add, VX_BINARY_BODY)
-DEF_VX_BINARY_CASE_1(uint64_t, -, sub, VX_BINARY_BODY)
-DEF_VX_BINARY_REVERSE_CASE_1(uint64_t, -, rsub, VX_BINARY_REVERSE_BODY);
+#define T uint64_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY);
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c
index 0da03d6225be..da51d0a1116b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c
@@ -3,9 +3,11 @@
#include "vx_binary.h"
-DEF_VX_BINARY_CASE_1(uint8_t, +, add, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_CASE_1(uint8_t, -, sub, VX_BINARY_BODY_X16)
-DEF_VX_BINARY_REVERSE_CASE_1(uint8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
+#define T uint8_t
+
+DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16);
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
