https://gcc.gnu.org/g:f168f75f0fa5d5e6fd2034c721d2919c75c84734
commit f168f75f0fa5d5e6fd2034c721d2919c75c84734
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue May 13 22:13:46 2025 -0400
Revert changes
Diff:
---
gcc/config/rs6000/predicates.md | 6 ++
gcc/config/rs6000/rs6000-protos.h | 17 +---
gcc/config/rs6000/rs6000.cc | 46 +++------
gcc/config/rs6000/rs6000.h | 10 +-
gcc/config/rs6000/rs6000.md | 99 +++++++++++++++----
gcc/testsuite/gcc.target/powerpc/pr118541.c | 141 ----------------------------
6 files changed, 103 insertions(+), 216 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 02ba8fa6c9b0..647e89afb6a7 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1463,6 +1463,12 @@
(define_predicate "fpmask_comparison_operator"
(match_code "eq,gt,ge"))
+;; Return 1 if OP is a comparison operator suitable for vector/scalar
+;; comparisons that generate a 0/-1 mask (i.e. the inverse of
+;; fpmask_comparison_operator).
+(define_predicate "invert_fpmask_comparison_operator"
+ (match_code "ne,unlt,unle"))
+
;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
;; comparisons that generate a -1/0 mask.
(define_predicate "vecint_comparison_operator"
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 5beb44fc339b..4619142d197b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -114,23 +114,8 @@ extern const char *rs6000_sibcall_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_call_template (rtx *, unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
-
-/* Whether we can reverse the sense of an ordered (UNLT, UNLE, UNGT, UNGE,
- UNEQ, or LTGT) comparison. If we are doing floating point conditional moves
- on power9 and above, we cannot convert an ordered comparison to unordered,
- since the instructions (XSCMP{EQ,GT,GE}DP) that are used for conditional
- moves can trap if an argument is a signalling NaN. However for normal jumps
- we can reverse a comparison since we only use unordered compare instructions
- which do not trap on signalling NaNs. */
-
-enum class rev_cond_ordered {
- ordered_ok,
- no_ordered
-};
-
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code,
- enum rev_cond_ordered);
+ enum rtx_code);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7e2dc33e26c5..74709bb4bc19 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15367,38 +15367,17 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode,
- enum rtx_code code,
- enum rev_cond_ordered ordered_cmp_ok)
+rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa.
-
- However, this is not safe for ordered comparisons (i.e. for isgreater,
- etc.) starting with the power9 because ifcvt.cc will want to create a fp
- cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of
- the arguments is a signalling NaN. */
-
- if (mode == CCFPmode)
- {
- /* If NaNs are allowed, don't allow the reversal of floating point
- comparisons when the comparison is used in the context of a floating
- point conditional move when no_ordered is passed. We do allow the
- comparsion to be reversed for explicit jumps when ordered_ok is
- passed. */
- if (!flag_finite_math_only)
- return (ordered_cmp_ok == rev_cond_ordered::no_ordered
- ? UNKNOWN
- : reverse_condition_maybe_unordered (code));
-
- /* Explicit ordered comparisons can be reversed if NaNs are not
- allowed. */
- else if (code == UNLT || code == UNLE || code == UNGT || code == UNGE
- || code == UNEQ || code == LTGT)
- return reverse_condition_maybe_unordered (code);
- }
-
- return reverse_condition (code);
+ becomes an unordered compare and vice versa. */
+ if (mode == CCFPmode
+ && (!flag_finite_math_only
+ || code == UNLT || code == UNLE || code == UNGT || code == UNGE
+ || code == UNEQ || code == LTGT))
+ return reverse_condition_maybe_unordered (code);
+ else
+ return reverse_condition (code);
}
/* Check if C (as 64bit integer) can be rotated to a constant which constains
@@ -16008,14 +15987,11 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
rtx not_result = gen_reg_rtx (CCEQmode);
rtx not_op, rev_cond_rtx;
machine_mode cc_mode;
- rtx_code rev;
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev = rs6000_reverse_condition (cc_mode, cond_code,
- rev_cond_ordered::ordered_ok);
- rev_cond_rtx = gen_rtx_fmt_ee (rev, SImode, XEXP (condition_rtx, 0),
- const0_rtx);
+ rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
+ SImode, XEXP (condition_rtx, 0),
const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index cf51d904c5e4..9267612fbc9c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,17 +1812,11 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because at present it doesn't use the
- trapping FP comparisons (fcmpo).
-
- However, this is not safe for ordered comparisons (i.e. for isgreater, etc.)
- starting with the power9 because ifcvt.cc will want to create a fp cmove,
- and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of the
- arguments is a signalling NaN. */
+ trapping FP comparisons (fcmpo). */
#define REVERSIBLE_CC_MODE(MODE) 1
/* Given a condition code and a mode, return the inverse condition. */
-#define REVERSE_CONDITION(CODE, MODE) \
- rs6000_reverse_condition (MODE, CODE, rev_cond_ordered::no_ordered)
+#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
/* Target cpu costs. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d9c9db5f1919..65da0c653304 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5730,6 +5730,43 @@
[(set_attr "length" "8")
(set_attr "type" "vecperm")])
+;; Handle inverting the fpmask comparisons.
+(define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_invert_p9"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=&wa,wa")
+ (if_then_else:SFDF
+ (match_operator:CCFP 1 "invert_fpmask_comparison_operator"
+ [(match_operand:SFDF2 2 "vsx_register_operand" "wa,wa")
+ (match_operand:SFDF2 3 "vsx_register_operand" "wa,wa")])
+ (match_operand:SFDF 4 "vsx_register_operand" "wa,wa")
+ (match_operand:SFDF 5 "vsx_register_operand" "wa,wa")))
+ (clobber (match_scratch:V2DI 6 "=0,&wa"))]
+ "TARGET_P9_MINMAX"
+ "#"
+ "&& 1"
+ [(set (match_dup 6)
+ (if_then_else:V2DI (match_dup 9)
+ (match_dup 7)
+ (match_dup 8)))
+ (set (match_dup 0)
+ (if_then_else:SFDF (ne (match_dup 6)
+ (match_dup 8))
+ (match_dup 5)
+ (match_dup 4)))]
+{
+ rtx op1 = operands[1];
+ enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
+
+ if (GET_CODE (operands[6]) == SCRATCH)
+ operands[6] = gen_reg_rtx (V2DImode);
+
+ operands[7] = CONSTM1_RTX (V2DImode);
+ operands[8] = CONST0_RTX (V2DImode);
+
+ operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]);
+}
+ [(set_attr "length" "8")
+ (set_attr "type" "vecperm")])
+
(define_insn "*fpmask<mode>"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
(if_then_else:V2DI
@@ -5798,6 +5835,43 @@
[(set_attr "length" "8")
(set_attr "type" "vecperm")])
+;; Handle inverting the fpmask comparisons.
+(define_insn_and_split "*mov<mode>cc_invert_p10"
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=&v,v")
+ (if_then_else:IEEE128
+ (match_operator:CCFP 1 "invert_fpmask_comparison_operator"
+ [(match_operand:IEEE128 2 "altivec_register_operand" "v,v")
+ (match_operand:IEEE128 3 "altivec_register_operand" "v,v")])
+ (match_operand:IEEE128 4 "altivec_register_operand" "v,v")
+ (match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
+ (clobber (match_scratch:V2DI 6 "=0,&v"))]
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
+ "#"
+ "&& 1"
+ [(set (match_dup 6)
+ (if_then_else:V2DI (match_dup 9)
+ (match_dup 7)
+ (match_dup 8)))
+ (set (match_dup 0)
+ (if_then_else:IEEE128 (ne (match_dup 6)
+ (match_dup 8))
+ (match_dup 5)
+ (match_dup 4)))]
+{
+ rtx op1 = operands[1];
+ enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
+
+ if (GET_CODE (operands[6]) == SCRATCH)
+ operands[6] = gen_reg_rtx (V2DImode);
+
+ operands[7] = CONSTM1_RTX (V2DImode);
+ operands[8] = CONST0_RTX (V2DImode);
+
+ operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]);
+}
+ [(set_attr "length" "8")
+ (set_attr "type" "vecperm")])
+
(define_insn "*fpmask<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
(if_then_else:V2DI
@@ -13423,7 +13497,7 @@
;; If we are comparing the result of two comparisons, this can be done
;; using creqv or crxor.
-(define_insn_and_split "*reverse_branch_comparison"
+(define_insn_and_split ""
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
(compare:CCEQ (match_operator 1 "branch_comparison_operator"
[(match_operand 2 "cc_reg_operand" "y")
@@ -13438,7 +13512,6 @@
(match_dup 5)))]
{
int positive_1, positive_2;
- enum rev_cond_ordered order_ok = rev_cond_ordered::ordered_ok;
positive_1 = branch_positive_comparison_operator (operands[1],
GET_MODE (operands[1]));
@@ -13446,25 +13519,19 @@
GET_MODE (operands[3]));
if (! positive_1)
- {
- rtx_code rev = rs6000_reverse_condition (GET_MODE (operands[2]),
- GET_CODE (operands[1]),
- order_ok);
- gcc_assert (rev != UNKNOWN);
- operands[1] = gen_rtx_fmt_ee (rev, SImode, operands[2], const0_rtx);
- }
+ operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE
(operands[2]),
+ GET_CODE
(operands[1])),
+ SImode,
+ operands[2], const0_rtx);
else if (GET_MODE (operands[1]) != SImode)
operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
operands[2], const0_rtx);
if (! positive_2)
- {
- rtx_code rev = rs6000_reverse_condition (GET_MODE (operands[4]),
- GET_CODE (operands[3]),
- order_ok);
- gcc_assert (rev != UNKNOWN);
- operands[3] = gen_rtx_fmt_ee (rev, SImode, operands[4], const0_rtx);
- }
+ operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE
(operands[4]),
+ GET_CODE
(operands[3])),
+ SImode,
+ operands[4], const0_rtx);
else if (GET_MODE (operands[3]) != SImode)
operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
operands[4], const0_rtx);
diff --git a/gcc/testsuite/gcc.target/powerpc/pr118541.c
b/gcc/testsuite/gcc.target/powerpc/pr118541.c
deleted file mode 100644
index 80f1b2d2d83d..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr118541.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-/* { dg-require-effective-target powerpc_vsx } */
-
-/* PR target/118541 says that the ordered comparison functions like isgreater
- should not optimize floating point conditional moves to use
- x{s,v}cmp{eq,gt,ge}{dp,qp} and xxsel since that instruction can cause traps
- if one of the arguments is a signaling NaN. */
-
-/* Verify isgreater, isgreaterequal, isless, and islessequal does not generate
- xscmpltdp, xscmpgtdp, or xscmpeqdp. */
-
-double
-ordered_gt (double a, double b, double c, double d)
-{
- /*
- * fcmpu 0,1,2
- * fmr 1,4
- * bnglr 0
- * fmr 1,3
- * blr
- */
-
- return __builtin_isgreater (a, b) ? c : d;
-}
-
-double
-ordered_ge (double a, double b, double c, double d)
-{
- /*
- * fcmpu 0,1,2
- * fmr 1,4
- * cror 2,0,3
- * beqlr 0
- * fmr 1,3
- * blr
- */
-
- return __builtin_isgreaterequal (a, b) ? c : d;
-}
-
-double
-ordered_lt (double a, double b, double c, double d)
-{
- /*
- * fcmpu 0,1,2
- * fmr 1,4
- * bnllr 0
- * fmr 1,3
- * blr
- */
-
- return __builtin_isless (a, b) ? c : d;
-}
-
-double
-ordered_le (double a, double b, double c, double d)
-{
- /*
- * fcmpu 0,1,2
- * fmr 1,4
- * cror 2,1,3
- * beqlr 0
- * fmr 1,3
- * blr
- */
-
- return __builtin_islessequal (a, b) ? c : d;
-}
-
-double
-normal_gt (double a, double b, double c, double d)
-{
- /*
- * xscmpgtdp 1,1,2
- * xxsel 1,4,3,1
- * blr
- */
-
- return a > b ? c : d;
-}
-
-double
-normal_ge (double a, double b, double c, double d)
-{
- /*
- * xscmpgedp 1,1,2
- * xxsel 1,4,3,1
- * blr
- */
-
- return a >= b ? c : d;
-}
-
-double
-normal_lt (double a, double b, double c, double d)
-{
- /*
- * xscmpgtdp 1,2,1
- * xxsel 1,4,3,1
- * blr
- */
-
- return a < b ? c : d;
-}
-
-double
-normal_le (double a, double b, double c, double d)
-{
- /*
- * xscmpgedp 1,2,1
- * xxsel 1,4,3,1
- * blr
- */
-
- return a <= b ? c : d;
-}
-
-double
-normal_eq (double a, double b, double c, double d)
-{
- /*
- * xscmpeqdp 1,1,2
- * xxsel 1,4,3,1
- * blr
- */
-
- return a == b ? c : d;
-}
-
-double
-normal_ne (double a, double b, double c, double d)
-{
- /*
- * xscmpeqdp 1,1,2
- * xxsel 1,3,4,1
- * blr
- */
-
- return a != b ? c : d;
-}
