https://gcc.gnu.org/g:84e5dca3b374712d32fed999f11a57215a97705d
commit 84e5dca3b374712d32fed999f11a57215a97705d
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue May 13 19:57:44 2025 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.bugs | 177 +++++++++++++++++++++++++++--------------------------
1 file changed, 91 insertions(+), 86 deletions(-)
diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 3a3f9079e368..ff3eb7e1d34c 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,84 +1,7 @@
-==================== Branch work204-bugs, patch #102 ====================
-
-PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
-
-We had optimizations for splat of a vector extract for the other vector
-types, but we missed having one for V2DI and V2DF. This patch adds a
-combiner insn to do this optimization.
-
-In looking at the source, we had similar optimizations for V4SI and V4SF
-extract and splats, but we missed doing V2DI/V2DF.
-
-Without the patch for the code:
-
- vector long long splat_dup_l_0 (vector long long v)
- {
- return __builtin_vec_splats (__builtin_vec_extract (v, 0));
- }
-
-the compiler generates (on a little endian power9):
-
- splat_dup_l_0:
- mfvsrld 9,34
- mtvsrdd 34,9,9
- blr
-
-Now it generates:
-
- splat_dup_l_0:
- xxpermdi 34,34,34,3
- blr
-
-2025-04-30 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- PR target/99293
- * config/rs6000/vsx.md (vsx_splat_extract_<mode>): New insn.
-
-gcc/testsuite/
-
- PR target/99293
- * gcc.target/powerpc/builtins-1.c: Adjust insn count.
- * gcc.target/powerpc/pr99293.c: New test.
-
-==================== Branch work204-bugs, patch #101 ====================
-
-PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
-
-Previously GCC would zero externd a DImode GPR value to TImode by first zero
-extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
-move this value to a VSX register.
-
-This patch does the move directly, since if the middle argument to MTVSRDD is
0,
-it does the zero extend.
-
-If the DImode value is already in a vector register, it does a XXSPLTIB and
-XXPERMDI to get the value into the bottom 64-bits of the register.
-
-I have built GCC with the patches in this patch set applied on both little and
-big endian PowerPC systems and there were no regressions. Can I apply this
-patch to GCC 15?
-
-2025-04-30 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- PR target/108598
- * gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.
-
-gcc/testsuite/
-
- PR target/108598
- * gcc.target/powerpc/pr108958.c: New test.
-
-==================== Branch work204-bugs, patch #100 ====================
+==================== Branch work204-bugs, patch #110 ====================
Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.
-Bernhard Reutner-Fischer suggested some typos to the patch for 118551. Here
-is the changed patch.
-
In bug PR target/118541 on power9, power10, and power11 systems, for the
function:
@@ -120,13 +43,22 @@ raise an interrupt.
The following patch changes the PowerPC back end so that ifcvt.c will not
change
the if/then test and move into a conditional move if the comparison is one of
the comparisons that do not raise an error with signalling NaNs and -Ofast is
-not used. If a normal comparison is used or -Ofast is used, GCC will continue
-to generate XSCMPGTDP and XXSEL.
+not used. If a normal comparison is used, GCC will continue to generate
+XSCMPGTDP and XXSEL.
+
+In the previous version of the patch if -Ofast was used, isgreater and other
+IEEE comparison functions would generate the XSCMPGTDP and XSCMPGEDP
+instructions. This version of the patch just removes trying to invert using
+inverted fpmasks at all, and if UN{GT,GE,LT,LE} are generated, it will always
+fall back to doing a comparison and a jump.
+
+However if -ffinite-math-only (or -Ofast or -ffast-math) is used, the machine
+independent portion of the compiler will convert UNGT into GT, and in that case
+we will generate XSCMPGTDP, etc.
For the following code:
- double
- ordered_compare (double a, double b, double c, double d)
+ double ordered_compare (double a, double b, double c, double d)
{
return __builtin_isgreater (a, b) ? c : d;
}
@@ -179,10 +111,83 @@ gcc/
gcc/testsuite/
PR target/118541
- * gcc.target/powerpc/pr118541-1.c: New test.
- * gcc.target/powerpc/pr118541-2.c: Likewise.
- * gcc.target/powerpc/pr118541-3.c: Likewise.
- * gcc.target/powerpc/pr118541-4.c: Likewise.
+ * gcc.target/powerpc/pr118541.c: New test.
+
+==================== Branch work204-bugs, patch #102 ====================
+
+PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
+
+We had optimizations for splat of a vector extract for the other vector
+types, but we missed having one for V2DI and V2DF. This patch adds a
+combiner insn to do this optimization.
+
+In looking at the source, we had similar optimizations for V4SI and V4SF
+extract and splats, but we missed doing V2DI/V2DF.
+
+Without the patch for the code:
+
+ vector long long splat_dup_l_0 (vector long long v)
+ {
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+ }
+
+the compiler generates (on a little endian power9):
+
+ splat_dup_l_0:
+ mfvsrld 9,34
+ mtvsrdd 34,9,9
+ blr
+
+Now it generates:
+
+ splat_dup_l_0:
+ xxpermdi 34,34,34,3
+ blr
+
+2025-04-30 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ PR target/99293
+ * config/rs6000/vsx.md (vsx_splat_extract_<mode>): New insn.
+
+gcc/testsuite/
+
+ PR target/99293
+ * gcc.target/powerpc/builtins-1.c: Adjust insn count.
+ * gcc.target/powerpc/pr99293.c: New test.
+
+==================== Branch work204-bugs, patch #101 ====================
+
+PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
+
+Previously GCC would zero externd a DImode GPR value to TImode by first zero
+extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
+move this value to a VSX register.
+
+This patch does the move directly, since if the middle argument to MTVSRDD is
0,
+it does the zero extend.
+
+If the DImode value is already in a vector register, it does a XXSPLTIB and
+XXPERMDI to get the value into the bottom 64-bits of the register.
+
+I have built GCC with the patches in this patch set applied on both little and
+big endian PowerPC systems and there were no regressions. Can I apply this
+patch to GCC 15?
+
+2025-04-30 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ PR target/108598
+ * gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.
+
+gcc/testsuite/
+
+ PR target/108598
+ * gcc.target/powerpc/pr108958.c: New test.
+
+==================== Branch work204-bugs, patch #100 was reverted
====================
==================== Branch work204-bugs, baseline ====================
