https://gcc.gnu.org/g:0f74d1e38a7dd1931ab110c2b64b633393393437
commit r15-9336-g0f74d1e38a7dd1931ab110c2b64b633393393437
Author: Jeff Law <j...@ventanamicro.com>
Date: Wed Apr 9 07:55:06 2025 -0600
[committed][RISC-V] Adjust expected output for rvv test
The recent combine changes twiddled code generation ever so slightly on
risc-v
and is causing pr117722.c to fail.
The relevant change is this sequence to perform an abs() across elements in
a
vector:
> ! vwsubu.vv v1,v4,v3
> vsetvli zero,zero,e16,mf2,tu,ma
> - vrsub.vi v3,v1,0
> - vmax.vv v1,v1,v3
Turns into:
> ! vwsubu.vv v1,v3,v4
> ! vwsubu.vv v5,v4,v3
> vsetvli zero,zero,e16,mf2,tu,ma
> + vmax.vv v1,v1,v5
There's other trivial differences, but that highlights the key change in the
abs sequence.
The first sequence has lower register pressure since it synthesizes the
negation using vrsub.vi.
The second sequence is better from a data dependency standpoint as the two
vwsubu instructions can execute in parallel on designs with > 1 vector ALU.
I don't consider either sequence inherently better than the other. So I'm
just
adjusting the test to accept our new code.
gcc/testsuite
* gcc.target/riscv/rvv/autovec/pr117722.c: Adjust expected output.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c
index 493dab056212..02670784feaf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c
@@ -18,6 +18,5 @@ int pixel_sad_n(unsigned char *pix1, unsigned char *pix2, int
n)
return sum;
}
-/* { dg-final { scan-assembler {vrsub\.v} } } */
/* { dg-final { scan-assembler {vmax\.v} } } */
-/* { dg-final { scan-assembler {vwsubu\.v} } } */
+/* { dg-final { scan-assembler-times {vwsubu\.v} 2 } } */
