https://gcc.gnu.org/g:b6d3a23cb027eb48a01ee5d70c6c72ab3bcde467
commit r15-9170-gb6d3a23cb027eb48a01ee5d70c6c72ab3bcde467
Author: Alexandre Oliva <ol...@adacore.com>
Date: Thu Apr 3 03:06:47 2025 -0300
[testsuite] [riscv] limit mcpu-xiangshan-nanhu.c to rv64
The testcase makes the -march option conditional on rv64, and #errors
out if the desired CPU properties are not active. This makes the test
fail on rv32. Arrange to skip the test on rv32 instead, moving the
rv64 conditional.
for gcc/testsuite/ChangeLog
* gcc.target/riscv/mcpu-xiangshan-nanhu.c: Skip on non-rv64.
Diff:
---
gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c
b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c
index 2903c88d91c8..c2a374f54fc8 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c
@@ -1,6 +1,6 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
-/* { dg-options "-mcpu=xiangshan-nanhu" { target { rv64 } } } */
+/* { dg-options "-mcpu=xiangshan-nanhu" } */
/* XiangShan Nanhu => rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd
_zkne_zknh_zksed_zksh_svinval_zicbom_zicboz */
