https://gcc.gnu.org/g:5c77379695b8441619ccef0f509fc3781d9bec69
commit 5c77379695b8441619ccef0f509fc3781d9bec69
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Apr 1 18:52:08 2025 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.bugs | 163 +++++++++++++++++++++++++++--------------------------
1 file changed, 84 insertions(+), 79 deletions(-)
diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 8ae245fe2af6..8d58af20d594 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,86 +1,15 @@
-==================== Branch work198-bugs, patch #202 ====================
-
-PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
-
-We had optimizations for splat of a vector extract for the other vector
-types, but we missed having one for V2DI and V2DF. This patch adds a
-combiner insn to do this optimization.
-
-In looking at the source, we had similar optimizations for V4SI and V4SF
-extract and splats, but we missed doing V2DI/V2DF.
-
-Without the patch for the code:
-
- vector long long splat_dup_l_0 (vector long long v)
- {
- return __builtin_vec_splats (__builtin_vec_extract (v, 0));
- }
-
-the compiler generates (on a little endian power9):
-
- splat_dup_l_0:
- mfvsrld 9,34
- mtvsrdd 34,9,9
- blr
-
-Now it generates:
-
- splat_dup_l_0:
- xxpermdi 34,34,34,3
- blr
-
-2025-03-27 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- PR target/99293
- * config/rs6000/vsx.md (vsx_splat_extract_<mode>): New insn.
-
-gcc/testsuite/
-
- PR target/99293
- * gcc.target/powerpc/builtins-1.c: Adjust insn count.
- * gcc.target/powerpc/pr99293.c: New test.
-
-==================== Branch work198-bugs, patch #201 ====================
-
-PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
-
-Previously GCC would zero externd a DImode GPR value to TImode by first zero
-extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
-move this value to a VSX register.
-
-This patch does the move directly, since if the middle argument to MTVSRDD is
0,
-it does the zero extend.
-
-If the DImode value is already in a vector register, it does a XXSPLTIB and
-XXPERMDI to get the value into the bottom 64-bits of the register.
-
-I have built GCC with the patches in this patch set applied on both little and
-big endian PowerPC systems and there were no regressions. Can I apply this
-patch to GCC 15?
-
-2025-03-27 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- PR target/108598
- * gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.
-
-gcc/testsuite/
-
- PR target/108598
- * gcc.target/powerpc/pr108958.c: New test.
-
-==================== Branch work198-bugs, patch #200 ====================
+==================== Branch work198-bugs, patch #210 ====================
Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.
-This is version 5 of the patch.
+This is version 6 of the patch.
-In versions 4 and 5, I made the following changes:
+In version 6 of the patch, I fixed some typos.
- 1: I changed the use of enums to match current C++.
+In version 5 of the patch, I added the 'class' keyword in declaring the
+enumeration.
+
+In versions 4 of the patch, I changed the use of enums to match current C++.
In version 3, I made the following changes:
@@ -176,7 +105,7 @@ power9/power10 systems and there were no regressions. Can
I check this patch
into the GCC trunk, and after a waiting period, can I check this into the
active
older branches?
-2025-03-27 Michael Meissner <meiss...@linux.ibm.com>
+2025-04-01 Michael Meissner <meiss...@linux.ibm.com>
gcc/
@@ -201,6 +130,82 @@ gcc/testsuite/
* gcc.target/powerpc/pr118541-3.c: Likewise.
* gcc.target/powerpc/pr118541-4.c: Likewise.
+==================== Branch work198-bugs, patch #202 ====================
+
+PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
+
+We had optimizations for splat of a vector extract for the other vector
+types, but we missed having one for V2DI and V2DF. This patch adds a
+combiner insn to do this optimization.
+
+In looking at the source, we had similar optimizations for V4SI and V4SF
+extract and splats, but we missed doing V2DI/V2DF.
+
+Without the patch for the code:
+
+ vector long long splat_dup_l_0 (vector long long v)
+ {
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+ }
+
+the compiler generates (on a little endian power9):
+
+ splat_dup_l_0:
+ mfvsrld 9,34
+ mtvsrdd 34,9,9
+ blr
+
+Now it generates:
+
+ splat_dup_l_0:
+ xxpermdi 34,34,34,3
+ blr
+
+2025-03-27 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ PR target/99293
+ * config/rs6000/vsx.md (vsx_splat_extract_<mode>): New insn.
+
+gcc/testsuite/
+
+ PR target/99293
+ * gcc.target/powerpc/builtins-1.c: Adjust insn count.
+ * gcc.target/powerpc/pr99293.c: New test.
+
+==================== Branch work198-bugs, patch #201 ====================
+
+PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
+
+Previously GCC would zero externd a DImode GPR value to TImode by first zero
+extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
+move this value to a VSX register.
+
+This patch does the move directly, since if the middle argument to MTVSRDD is
0,
+it does the zero extend.
+
+If the DImode value is already in a vector register, it does a XXSPLTIB and
+XXPERMDI to get the value into the bottom 64-bits of the register.
+
+I have built GCC with the patches in this patch set applied on both little and
+big endian PowerPC systems and there were no regressions. Can I apply this
+patch to GCC 15?
+
+2025-03-27 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ PR target/108598
+ * gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.
+
+gcc/testsuite/
+
+ PR target/108598
+ * gcc.target/powerpc/pr108958.c: New test.
+
+==================== Branch work198-bugs, patch #200 was reverted
====================
+
==================== Branch work198-bugs, baseline ====================
Add ChangeLog.bugs and update REVISION.
