https://gcc.gnu.org/g:088ed1042d12f23261bc499b927b93fd61f8d574
commit r15-8977-g088ed1042d12f23261bc499b927b93fd61f8d574
Author: Richard Biener <rguent...@suse.de>
Date: Thu Mar 27 08:40:32 2025 +0100
target/119010 - add znver{4,5}_insn_both to resolve missing reservations
I still was seeing
;; 0--> b 0: i 101 {[sp-0x3c]=[sp-0x3c]+0x1;clobber flags;}:nothing
so the following adds a standard alu insn reservation mimicing that
from the znver.md description allowing both load and store.
PR target/119010
* config/i386/zn4zn5.md (znver4_insn_both, znver5_insn_both):
New reservation for ALU ops with load and store.
Diff:
---
gcc/config/i386/zn4zn5.md | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md
index 5a3960e9d010..75e310202150 100644
--- a/gcc/config/i386/zn4zn5.md
+++ b/gcc/config/i386/zn4zn5.md
@@ -421,6 +421,18 @@
(eq_attr "memory" "store")))
"znver4-direct,znver4-ieu,znver5-store")
+(define_insn_reservation "znver4_insn_both" 5
+ (and (eq_attr "cpu" "znver4")
+ (and (eq_attr "type"
"alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp")
+ (eq_attr "memory" "both")))
+ "znver4-direct,znver4-load,znver4-ieu,znver4-store")
+
+(define_insn_reservation "znver5_insn_both" 5
+ (and (eq_attr "cpu" "znver5")
+ (and (eq_attr "type"
"alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp")
+ (eq_attr "memory" "both")))
+ "znver4-direct,znver5-load,znver4-ieu,znver5-store")
+
(define_insn_reservation "znver4_insn2_store" 1
(and (eq_attr "cpu" "znver4")
(and (eq_attr "type" "icmov,setcc")
