[gcc r15-8919] target/119010 - add missing integer store reservations for znver4 and znver5

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:c3a704df22f11f4d337fa5d73c642a6f7a96d6f2

commit r15-8919-gc3a704df22f11f4d337fa5d73c642a6f7a96d6f2
Author: Richard Biener <rguent...@suse.de>
Date:   Tue Mar 25 15:40:22 2025 +0100

    target/119010 - add missing integer store reservations for znver4 and znver5
    
    The imov and imovx classified stores miss reservations in the znver4/5
    pipeline description.  The following adds them.
    
            PR target/119010
            * config/i386/zn4zn5.md (znver4_imov_double_store,
            znver5_imov_double_store, znver4_imov_store, znver5_imov_store):
            New reservations for integer stores.

Diff:
---
 gcc/config/i386/zn4zn5.md | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md
index ae188a1201e5..bc7712db6288 100644
--- a/gcc/config/i386/zn4zn5.md
+++ b/gcc/config/i386/zn4zn5.md
@@ -142,6 +142,20 @@
                                   (eq_attr "memory" "load"))))
                         "znver4-double,znver5-load,znver5-ieu")
 
+(define_insn_reservation "znver4_imov_double_store" 5
+                       (and (eq_attr "cpu" "znver4")
+                                (and (eq_attr "znver1_decode" "double")
+                                 (and (eq_attr "type" "imov")
+                                  (eq_attr "memory" "store"))))
+                        "znver4-double,znver4-store,znver4-ieu")
+
+(define_insn_reservation "znver5_imov_double_store" 5
+                       (and (eq_attr "cpu" "znver5")
+                                (and (eq_attr "znver1_decode" "double")
+                                 (and (eq_attr "type" "imov")
+                                  (eq_attr "memory" "store"))))
+                        "znver4-double,znver5-store,znver5-ieu")
+
 ;; imov, imovx
 (define_insn_reservation "znver4_imov" 1
             (and (eq_attr "cpu" "znver4")
@@ -167,6 +181,18 @@
                                  (eq_attr "memory" "load")))
                         "znver4-direct,znver5-load,znver5-ieu")
 
+(define_insn_reservation "znver4_imov_store" 5
+                       (and (eq_attr "cpu" "znver4")
+                                (and (eq_attr "type" "imov,imovx")
+                                 (eq_attr "memory" "store")))
+                        "znver4-direct,znver4-store,znver4-ieu")
+
+(define_insn_reservation "znver5_imov_store" 5
+                       (and (eq_attr "cpu" "znver5")
+                                (and (eq_attr "type" "imov,imovx")
+                                 (eq_attr "memory" "store")))
+                        "znver4-direct,znver5-store,znver5-ieu")
+
 ;; Push Instruction
 (define_insn_reservation "znver4_push" 1
                        (and (eq_attr "cpu" "znver4")