https://gcc.gnu.org/g:9798ba2c6b4cccb17277a9d5fc04d285bf48f742
commit r15-7884-g9798ba2c6b4cccb17277a9d5fc04d285bf48f742
Author: Tamar Christina <tamar.christ...@arm.com>
Date: Fri Mar 7 13:32:11 2025 +0000
aarch64: add support for partial modes to last extractions [PR118464]
The last extraction instructions work full both full and partial SVE
vectors,
however we currrently only define them for FULL vectors.
Early break code for VLA now however requires partial vector support, which
relies on extract_last support.
I have not added any new testcases as they overlap with the existing Early
break tests which now fail without this.
gcc/ChangeLog:
PR tree-optimization/118464
PR tree-optimization/116855
* config/aarch64/aarch64-sve.md (@extract_<last_op>_<mode>,
@fold_extract_<last_op>_<mode>,
@aarch64_fold_extract_vector_<last_op>_<mode>): Change SVE_FULL to
SVE_ALL.
* config/aarch64/iterators.md (vccore): Add more partial types.
Diff:
---
gcc/config/aarch64/aarch64-sve.md | 24 ++++++++++++------------
gcc/config/aarch64/iterators.md | 6 +++++-
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index a93bc463a909..3dbd65986ec7 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3107,12 +3107,12 @@
[(set (match_operand:<VEL> 0 "register_operand")
(unspec:<VEL>
[(match_operand:<VPRED> 1 "register_operand")
- (match_operand:SVE_FULL 2 "register_operand")]
+ (match_operand:SVE_ALL 2 "register_operand")]
LAST))]
"TARGET_SVE"
{@ [ cons: =0 , 1 , 2 ]
- [ ?r , Upl , w ] last<ab>\t%<vwcore>0, %1, %2.<Vetype>
- [ w , Upl , w ] last<ab>\t%<Vetype>0, %1, %2.<Vetype>
+ [ ?r , Upl , w ] last<ab>\t%<vccore>0, %1, %2.<Vctype>
+ [ w , Upl , w ] last<ab>\t%<Vctype>0, %1, %2.<Vctype>
}
)
@@ -8899,26 +8899,26 @@
(unspec:<VEL>
[(match_operand:<VEL> 1 "register_operand")
(match_operand:<VPRED> 2 "register_operand")
- (match_operand:SVE_FULL 3 "register_operand")]
+ (match_operand:SVE_ALL 3 "register_operand")]
CLAST))]
"TARGET_SVE"
{@ [ cons: =0 , 1 , 2 , 3 ]
- [ ?r , 0 , Upl , w ] clast<ab>\t%<vwcore>0, %2, %<vwcore>0,
%3.<Vetype>
- [ w , 0 , Upl , w ] clast<ab>\t%<Vetype>0, %2, %<Vetype>0,
%3.<Vetype>
+ [ ?r , 0 , Upl , w ] clast<ab>\t%<vccore>0, %2, %<vccore>0,
%3.<Vctype>
+ [ w , 0 , Upl , w ] clast<ab>\t%<Vctype>0, %2, %<Vctype>0,
%3.<Vctype>
}
)
(define_insn "@aarch64_fold_extract_vector_<last_op>_<mode>"
- [(set (match_operand:SVE_FULL 0 "register_operand")
- (unspec:SVE_FULL
- [(match_operand:SVE_FULL 1 "register_operand")
+ [(set (match_operand:SVE_ALL 0 "register_operand")
+ (unspec:SVE_ALL
+ [(match_operand:SVE_ALL 1 "register_operand")
(match_operand:<VPRED> 2 "register_operand")
- (match_operand:SVE_FULL 3 "register_operand")]
+ (match_operand:SVE_ALL 3 "register_operand")]
CLAST))]
"TARGET_SVE"
{@ [ cons: =0 , 1 , 2 , 3 ]
- [ w , 0 , Upl , w ] clast<ab>\t%0.<Vetype>, %2, %0.<Vetype>,
%3.<Vetype>
- [ ?&w , w , Upl , w ] movprfx\t%0, %1\;clast<ab>\t%0.<Vetype>, %2,
%0.<Vetype>, %3.<Vetype>
+ [ w , 0 , Upl , w ] clast<ab>\t%0.<Vctype>, %2, %0.<Vctype>,
%3.<Vctype>
+ [ ?&w , w , Upl , w ] movprfx\t%0, %1\;clast<ab>\t%0.<Vctype>, %2,
%0.<Vctype>, %3.<Vctype>
}
)
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 5bfd6e7d362a..146453b05168 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2025,8 +2025,12 @@
;; Like vwcore, but for the container mode rather than the element mode.
(define_mode_attr vccore [(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "x")
(VNx8HI "w") (VNx4HI "w") (VNx2HI "x")
+ (VNx8HF "w") (VNx4HF "w") (VNx2HF "x")
+ (VNx8BF "w") (VNx4BF "w") (VNx2BF "x")
(VNx4SI "w") (VNx2SI "x")
- (VNx2DI "x")])
+ (VNx4SF "w") (VNx2SF "x")
+ (VNx2DI "x")
+ (VNx2DF "x")])
;; Double vector types for ALLX.
(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
