https://gcc.gnu.org/g:316eaca17ee11f575fc72e139e8cc3f9f5ccb067
commit r15-7847-g316eaca17ee11f575fc72e139e8cc3f9f5ccb067
Author: Jeff Law <j...@ventanamicro.com>
Date: Wed Mar 5 22:24:05 2025 -0700
Improve coverage of ext-dce tests in risc-v testsuite
Inspired by Liao Shihua, this adjusts two tests in the RISC-V testsuite
to get more coverage. Drop the -O1 argument and replace it with -fext-dce.
That way the test gets run across the full set of flags. We just need to
make sure to skip -O0.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/core_list_init.c: Use -fext-dce rather than
-O1. Skip for -O0.
* gcc.target/riscv/pr111384.c: Ditto.
Diff:
---
gcc/testsuite/gcc.target/riscv/core_list_init.c | 3 ++-
gcc/testsuite/gcc.target/riscv/pr111384.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/core_list_init.c
b/gcc/testsuite/gcc.target/riscv/core_list_init.c
index 2f36dae85aa7..eec3a817d80c 100644
--- a/gcc/testsuite/gcc.target/riscv/core_list_init.c
+++ b/gcc/testsuite/gcc.target/riscv/core_list_init.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -fdump-rtl-ext_dce" } */
+/* { dg-options "-fext-dce -fdump-rtl-ext_dce" } */
/* { dg-final { scan-rtl-dump {Successfully transformed} "ext_dce" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0"} } */
unsigned short
core_list_init (int size, short seed) {
diff --git a/gcc/testsuite/gcc.target/riscv/pr111384.c
b/gcc/testsuite/gcc.target/riscv/pr111384.c
index a4e77d4aeb64..0000bcf33ebf 100644
--- a/gcc/testsuite/gcc.target/riscv/pr111384.c
+++ b/gcc/testsuite/gcc.target/riscv/pr111384.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -fdump-rtl-ext_dce" } */
+/* { dg-options "-fext-dce -fdump-rtl-ext_dce" } */
/* { dg-final { scan-rtl-dump {Successfully transformed} "ext_dce" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0"} } */
void
foo(unsigned int src, unsigned short *dst1, unsigned short *dst2)
