[gcc r15-7787] [RISC-V][PR target/118934] Fix ICE in RISC-V long branch support

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:67e824c2497176980cb0c5d14bc730fa4ce2e1ad

commit r15-7787-g67e824c2497176980cb0c5d14bc730fa4ce2e1ad
Author: Jeff Law <j...@ventanamicro.com>
Date:   Sun Mar 2 12:08:34 2025 -0700

    [RISC-V][PR target/118934] Fix ICE in RISC-V long branch support
    
    I'm not sure if I goof'd this or if I merely upstreamed someone else's goof.
    Either way the long branch code isn't working correctly.
    
    We were using 'n' as the output modifier to negate the condition.  But 'n' 
has
    a special meaning elsewhere, so when presented with a condition rather than
    what was expected, boom, the compiler ICE'd.
    
    Thankfully there's only a few places where we were using %n which I turned 
into
    %r.
    
    The BZ entry includes a good testcase, it just takes a long time to compile 
as
    it's trying to create the out-of-range scenario.  I'm not including the
    testcase due to how long it takes, but I did test it locally to ensure it's
    working properly now.
    
    I'm sure that with a little bit of work I could create at testcase that 
worked
    before and fails with the trunk (by taking advantage of the fuzzyness in 
length
    computations).  So I'm going to consider this a regression.
    
    Will push to the trunk after pre-commit testing does its thing.
    
            PR target/118934
    gcc/
            * config/riscv/corev.md (cv_branch): Adjust output template.
            (branch): Likewise.
            * config/riscv/riscv.md (branch): Likewise.
            * config/riscv/riscv.cc (riscv_asm_output_opcode): Handle 'r' rather
            than 'n'.

Diff:
---
 gcc/config/riscv/corev.md | 4 ++--
 gcc/config/riscv/riscv.cc | 4 ++--
 gcc/config/riscv/riscv.md | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index e44fdc1129dd..1d4eb84c3e70 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -2627,7 +2627,7 @@
   "TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "cv.b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "cv.b%r1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "cv.b%C1imm\t%2,%3,%0";
 }
@@ -2645,7 +2645,7 @@
   "TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "b%r1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "b%C1\t%2,%z3,%l0";
 }
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 89aa25d5da92..38f3ae7cd840 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6868,7 +6868,7 @@ riscv_asm_output_opcode (FILE *asm_out_file, const char 
*p)
          any outermost HIGH.
    'R' Print the low-part relocation associated with OP.
    'C' Print the integer branch condition for comparison OP.
-   'n' Print the inverse of the integer branch condition for comparison OP.
+   'r' Print the inverse of the integer branch condition for comparison OP.
    'A' Print the atomic operation suffix for memory model OP.
    'I' Print the LR suffix for memory model OP.
    'J' Print the SC suffix for memory model OP.
@@ -7027,7 +7027,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       fputs (GET_RTX_NAME (code), file);
       break;
 
-    case 'n':
+    case 'r':
       /* The RTL names match the instruction names. */
       fputs (GET_RTX_NAME (reverse_condition (code)), file);
       break;
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f7070766783e..95951605fb46 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3252,7 +3252,7 @@
   "!TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "b%r1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "b%C1\t%2,%z3,%l0";
 }