https://gcc.gnu.org/g:a0d29dd218e7d96f0715360a2ab6fdd8dc9b3446
commit r15-7774-ga0d29dd218e7d96f0715360a2ab6fdd8dc9b3446
Author: Yuriy Kolerov <yuriy.kole...@synopsys.com>
Date: Sat Mar 1 08:35:55 2025 -0700
[PR target/118906] [PATCH v2] RISC-V: Fix a typo in zce to zcf implication
zce must imply zcf but this rule was corrupted after
refactoring in 9e12010b5e724277ea. This may be observed
ater generating an .s file from any source code file with
-mriscv-attribute -march=rv32if_zce -mabi=ilp32 -S
options. A full march will be presented in arch attribute:
rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0
As you see, zcf is not presented here though f_zce pair is
passed in -march. According to The RISC-V Instruction
Set Manual:
Specifying Zce on RV32 with F includes Zca, Zcb, Zcmp,
Zcmt and Zcf.
PR target/118906
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: fix zce to zcf
implication.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/attribute-zce-1.c: New test.
* gcc.target/riscv/attribute-zce-2.c: New test.
* gcc.target/riscv/attribute-zce-3.c: New test.
* gcc.target/riscv/attribute-zce-4.c: New test.
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 2 +-
gcc/testsuite/gcc.target/riscv/attribute-zce-1.c | 6 ++++++
gcc/testsuite/gcc.target/riscv/attribute-zce-2.c | 6 ++++++
gcc/testsuite/gcc.target/riscv/attribute-zce-3.c | 6 ++++++
gcc/testsuite/gcc.target/riscv/attribute-zce-4.c | 6 ++++++
5 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 5038f0eb959a..b34409adf39c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -213,7 +213,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zcmp", "zca"},
{"zcmt", "zca"},
{"zcmt", "zicsr"},
- {"zcf", "f",
+ {"zce", "zcf",
[] (const riscv_subset_list *subset_list) -> bool
{
return subset_list->xlen () == 32 && subset_list->lookup ("f");
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c
b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c
new file mode 100644
index 000000000000..e477414d4d5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv32i_zce -mabi=ilp32" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c
b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c
new file mode 100644
index 000000000000..7008eb5ea1fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv32if_zce -mabi=ilp32" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c
b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c
new file mode 100644
index 000000000000..89ebaaf40639
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_zce -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c
b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c
new file mode 100644
index 000000000000..cacbcaac35f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64if_zce -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */
