https://gcc.gnu.org/g:ba488a332ad171eff17c1f135c111c5730f4ce25
commit r14-11345-gba488a332ad171eff17c1f135c111c5730f4ce25
Author: Haochen Jiang <haochen.ji...@intel.com>
Date: Wed Feb 26 11:28:45 2025 +0800
i386: Treat Granite Rapids/Granite Rapids-D similar as Sapphire Rapids in
x86-tune.def
Since GNR, GNR-D are both P-core based, we should treat them
just like SPR for now.
gcc/ChangeLog:
* config/i386/x86-tune.def
(X86_TUNE_DEST_FALSE_DEP_FOR_GLC): Add GNR, GNR-D.
(X86_TUNE_AVOID_256FMA_CHAINS): Ditto.
(X86_TUNE_AVX512_MOVE_BY_PIECES): Ditto.
(X86_TUNE_AVX512_STORE_BY_PIECES): Ditto.
Diff:
---
gcc/config/i386/x86-tune.def | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index ec8de3144a8c..39431e07e69c 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -87,8 +87,8 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY,
several insns to break false dependency on the dest register for GLC
micro-architecture. */
DEF_TUNE (X86_TUNE_DEST_FALSE_DEP_FOR_GLC,
- "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_CORE_HYBRID
- | m_CORE_ATOM)
+ "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_GRANITERAPIDS
+ | m_GRANITERAPIDS_D | m_CORE_HYBRID | m_CORE_ATOM)
/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
are resolved on SSE register parts instead of whole registers, so we may
@@ -529,7 +529,8 @@ DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains",
m_ZNVER
smaller FMA chain. */
DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains",
m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_CORE_HYBRID
- | m_SAPPHIRERAPIDS | m_CORE_ATOM | m_GENERIC)
+ | m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
+ | m_CORE_ATOM | m_GENERIC)
/* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
smaller FMA chain. */
@@ -596,12 +597,14 @@ DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES,
"avx256_store_by_pieces",
/* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
AVX instructions. */
DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
- m_SAPPHIRERAPIDS | m_ZNVER4 | m_ZNVER5)
+ m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
+ | m_ZNVER4 | m_ZNVER5)
/* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
AVX instructions. */
DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
- m_SAPPHIRERAPIDS | m_ZNVER4 | m_ZNVER5)
+ m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
+ | m_ZNVER4 | m_ZNVER5)
/*****************************************************************************/
/*****************************************************************************/
