https://gcc.gnu.org/g:ab9518d0814a3b094a0ca7356b4a68e3a65f5011
commit r14-11294-gab9518d0814a3b094a0ca7356b4a68e3a65f5011
Author: Jakub Jelinek <ja...@redhat.com>
Date: Thu Feb 6 15:39:18 2025 +0100
loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506]
The following test ICEs on RISC-V at least latently since
r14-1622-g99bfdb072e67fa3fe294d86b4b2a9f686f8d9705 which added
RISC-V specific case to get_biv_step_1 to recognize also
({zero,sign}_extend:DI (plus:SI op0 op1))
The reason for the ICE is that op1 in this case is CONST_POLY_INT
which unlike the really expected VOIDmode CONST_INTs has its own
mode and still satisfies CONSTANT_P.
GET_MODE (rhs) (SImode) is different from outer_mode (DImode), so
the function later does
*inner_step = simplify_gen_binary (code, outer_mode,
*inner_step, op1);
but that obviously ICEs because while *inner_step is either VOIDmode
or DImode, op1 has SImode.
The following patch fixes it by extending op1 using code so that
simplify_gen_binary can handle it. Another option would be
to change the !CONSTANT_P (op1) 3 lines above this to
!CONST_INT_P (op1), I think it isn't very likely that we get something
useful from other constants there.
2025-02-06 Jakub Jelinek <ja...@redhat.com>
PR rtl-optimization/117506
* loop-iv.cc (get_biv_step_1): For {ZERO,SIGN}_EXTEND
of PLUS apply {ZERO,SIGN}_EXTEND to op1.
* gcc.dg/pr117506.c: New test.
* gcc.target/riscv/pr117506.c: New test.
(cherry picked from commit bb9cee8928f7f4dfb94e7a8f232eda736b711450)
Diff:
---
gcc/loop-iv.cc | 1 +
gcc/testsuite/gcc.dg/pr117506.c | 18 ++++++++++++++++++
gcc/testsuite/gcc.target/riscv/pr117506.c | 5 +++++
3 files changed, 24 insertions(+)
diff --git a/gcc/loop-iv.cc b/gcc/loop-iv.cc
index f56cc5e1db67..433a75cdb18b 100644
--- a/gcc/loop-iv.cc
+++ b/gcc/loop-iv.cc
@@ -714,6 +714,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx
reg,
if (!simple_reg_p (op0) || !CONSTANT_P (op1))
return false;
+ op1 = simplify_gen_unary (code, outer_mode, op1, GET_MODE (rhs));
prev_code = code;
code = PLUS;
}
diff --git a/gcc/testsuite/gcc.dg/pr117506.c b/gcc/testsuite/gcc.dg/pr117506.c
new file mode 100644
index 000000000000..4f25324645b8
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr117506.c
@@ -0,0 +1,18 @@
+/* PR rtl-optimization/117506 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -funroll-loops" } */
+
+char a;
+int b;
+unsigned c;
+short d;
+
+void
+foo ()
+{
+ for (short f = 0; f < c; f += 3)
+ {
+ a ^= d;
+ b = b < 0 ? b : 0;
+ }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/pr117506.c
b/gcc/testsuite/gcc.target/riscv/pr117506.c
new file mode 100644
index 000000000000..ac4b9e35d635
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr117506.c
@@ -0,0 +1,5 @@
+/* PR rtl-optimization/117506 */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64im_zve64f -mabi=lp64 -O3 -funroll-loops" } */
+
+#include "../../gcc.dg/pr117506.c"
