https://gcc.gnu.org/g:88bb18ccd87d43abe401a1228cc337e4b46be88d
commit r15-7333-g88bb18ccd87d43abe401a1228cc337e4b46be88d
Author: John David Anglin <dang...@gcc.gnu.org>
Date: Mon Feb 3 11:35:38 2025 -0500
hppa: Revise various millicode insn patterns to use match_operand
LRA does not correctly support hard-register input operands that
are clobbered. This is needed to support millicode calls on hppa.
The operand setup is sometimes deleted.
This problem can be avoided by hiding hard-register input operands
using match_operand. This also potentially allows for constraints
that specify the operand is both read and written.
2025-02-03 John David Anglin <dang...@gcc.gnu.org>
gcc/ChangeLog:
PR rtl-optimization/117248
* config/pa/predicates.md (r25_operand): New predicate.
(r26_operand): Likewise.
* config/pa/pa.md: Use match_operand for r25 and r26 hard
register operands in mult, div, udiv, mod and umod millicode
patterns.
Diff:
---
gcc/config/pa/pa.md | 56 +++++++++++++++++++++++++++++----------------
gcc/config/pa/predicates.md | 16 +++++++++++++
2 files changed, 52 insertions(+), 20 deletions(-)
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index df1b61e871f1..23129940e644 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5632,8 +5632,10 @@
(set_attr "length" "4")])
(define_insn ""
- [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_operand:SI 0 "register_operand" "=a"))
+ [(set (reg:SI 29)
+ (mult:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "r25_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5645,8 +5647,10 @@
(symbol_ref "pa_attr_length_millicode_call (insn)")))])
(define_insn ""
- [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_operand:SI 0 "register_operand" "=a"))
+ [(set (reg:SI 29)
+ (mult:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "r25_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5753,8 +5757,9 @@
(define_insn ""
[(set (reg:SI 29)
- (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
- (clobber (match_operand:SI 1 "register_operand" "=a"))
+ (div:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "div_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5768,8 +5773,9 @@
(define_insn ""
[(set (reg:SI 29)
- (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
- (clobber (match_operand:SI 1 "register_operand" "=a"))
+ (div:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "div_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5800,8 +5806,9 @@
(define_insn ""
[(set (reg:SI 29)
- (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
- (clobber (match_operand:SI 1 "register_operand" "=a"))
+ (udiv:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "div_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5815,8 +5822,9 @@
(define_insn ""
[(set (reg:SI 29)
- (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
- (clobber (match_operand:SI 1 "register_operand" "=a"))
+ (udiv:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "div_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5844,8 +5852,10 @@
}")
(define_insn ""
- [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_operand:SI 0 "register_operand" "=a"))
+ [(set (reg:SI 29)
+ (mod:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "r25_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5858,8 +5868,10 @@
(symbol_ref "pa_attr_length_millicode_call (insn)")))])
(define_insn ""
- [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_operand:SI 0 "register_operand" "=a"))
+ [(set (reg:SI 29)
+ (mod:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "r25_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5887,8 +5899,10 @@
}")
(define_insn ""
- [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_operand:SI 0 "register_operand" "=a"))
+ [(set (reg:SI 29)
+ (umod:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "r25_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5901,8 +5915,10 @@
(symbol_ref "pa_attr_length_millicode_call (insn)")))])
(define_insn ""
- [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_operand:SI 0 "register_operand" "=a"))
+ [(set (reg:SI 29)
+ (umod:SI (match_operand:SI 1 "r26_operand" "")
+ (match_operand:SI 0 "r25_operand" "")))
+ (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index 24bb1ac8646f..b0f8274ff798 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -191,6 +191,22 @@
&& CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
})
+;; True iff OP is a SImode r25 register operand.
+
+(define_predicate "r25_operand"
+ (match_code "reg")
+{
+ return mode == SImode && REG_P (op) && REGNO (op) == 25;
+})
+
+;; True iff OP is a SImode r26 register operand.
+
+(define_predicate "r26_operand"
+ (match_code "reg")
+{
+ return mode == SImode && REG_P (op) && REGNO (op) == 26;
+})
+
;; True iff OP can be used as the divisor in a div millicode call.
(define_predicate "div_operand"
