[gcc r15-6903] [RISC-V][PR target/118170] Add HF div/sqrt reservation

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:d6f1961e68092fda35ce064ef45d1dbec780c624

commit r15-6903-gd6f1961e68092fda35ce064ef45d1dbec780c624
Author: Anton Blanchard <ant...@tenstorrent.com>
Date:   Tue Jan 14 22:11:13 2025 -0700

    [RISC-V][PR target/118170] Add HF div/sqrt reservation
    
    Clearly an oversight in the generic-ooo model caught by the checking code.  
I
    should have realized it was generic-ooo as we don't have a pipeline 
description
    for the tenstorrent design yet, just the costing model.
    
    The patch was extracted from the BZ which indicated Anton was the author, 
so I
    kept that.  I'm listed as co-author just in case someone wants to complain
    about the testcase in the future.  I didn't do any notable lifting here.
    
    Thanks Peter and Anton!
    
            PR target/118170
    gcc/
            * config/riscv/generic-ooo.md (generic_ooo_float_div_half): New
            reservation.
    
    gcc/testsuite
            * gcc.target/riscv/pr118170.c: New test.
    
    Co-authored-by: Jeff Law <j...@ventanamicro.com>

Diff:
---
 gcc/config/riscv/generic-ooo.md           | 6 ++++++
 gcc/testsuite/gcc.target/riscv/pr118170.c | 9 +++++++++
 2 files changed, 15 insertions(+)

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 6cf3463cc42d..ae9430e47598 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -145,6 +145,12 @@
   "generic_ooo_issue,generic_ooo_fxu")
 
 ;; Assume float division and sqrt are not pipelined.
+(define_insn_reservation "generic_ooo_float_div_half" 10
+  (and (eq_attr "tune" "generic_ooo")
+       (and (eq_attr "type" "fdiv,fsqrt")
+           (eq_attr "mode" "HF")))
+  "generic_ooo_issue,generic_ooo_fxu,generic_ooo_div,generic_ooo_div*3")
+
 (define_insn_reservation "generic_ooo_float_div_single" 12
   (and (eq_attr "tune" "generic_ooo")
        (and (eq_attr "type" "fdiv,fsqrt")
diff --git a/gcc/testsuite/gcc.target/riscv/pr118170.c 
b/gcc/testsuite/gcc.target/riscv/pr118170.c
new file mode 100644
index 000000000000..306ff888aebd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr118170.c
@@ -0,0 +1,9 @@
+/* { dg-do "compile" } */
+/* { dg-options "-O2 -mcpu=tt-ascalon-d8" } */
+_Float16 f;
+
+void
+foo ()
+{
+  f /= 3;
+}