https://gcc.gnu.org/g:2c8913576fa0bf234bde3c9c1f137a1b9cca95f1
commit r15-6781-g2c8913576fa0bf234bde3c9c1f137a1b9cca95f1
Author: Andrew Carlotti <andrew.carlo...@arm.com>
Date: Thu Aug 1 11:54:41 2024 +0100
aarch64: Add new +jscvt flag
gcc/ChangeLog:
* config/aarch64/aarch64-arches.def (V8_3A): Add JSCVT.
* config/aarch64/aarch64-option-extensions.def (JSCVT): New flag.
* config/aarch64/aarch64.h (TARGET_JSCVT): Use new flag.
* config/aarch64/arm_acle.h: Use new flag for jscvt intrinsics.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/cpunative/native_cpu_21.c: Add jscvt to
expected feature string.
* gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto.
Diff:
---
gcc/config/aarch64/aarch64-arches.def | 2 +-
gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
gcc/config/aarch64/aarch64.h | 2 +-
gcc/config/aarch64/arm_acle.h | 2 +-
gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c | 2 +-
gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c | 2 +-
6 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-arches.def
b/gcc/config/aarch64/aarch64-arches.def
index d85b14be4c3f..a21e5de496e9 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -33,7 +33,7 @@
AARCH64_ARCH("armv8-a", generic_armv8_a, V8A, 8, (SIMD))
AARCH64_ARCH("armv8.1-a", generic_armv8_a, V8_1A, 8, (V8A, LSE,
CRC, RDMA))
AARCH64_ARCH("armv8.2-a", generic_armv8_a, V8_2A, 8, (V8_1A))
-AARCH64_ARCH("armv8.3-a", generic_armv8_a, V8_3A, 8, (V8_2A, PAUTH,
RCPC, FCMA))
+AARCH64_ARCH("armv8.3-a", generic_armv8_a, V8_3A, 8, (V8_2A, PAUTH,
RCPC, FCMA, JSCVT))
AARCH64_ARCH("armv8.4-a", generic_armv8_a, V8_4A, 8, (V8_3A,
F16FML, DOTPROD, FLAGM))
AARCH64_ARCH("armv8.5-a", generic_armv8_a, V8_5A, 8, (V8_4A, SB,
SSBS, PREDRES))
AARCH64_ARCH("armv8.6-a", generic_armv8_a, V8_6A, 8, (V8_5A, I8MM,
BF16))
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
b/gcc/config/aarch64/aarch64-option-extensions.def
index c41c4998c5cb..96518eeeeba6 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -151,6 +151,8 @@ AARCH64_OPT_EXTENSION("fp16fml", F16FML, (), (F16), (),
"asimdfhm")
AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML))
+AARCH64_OPT_FMV_EXTENSION("jscvt", JSCVT, (FP), (), (), "jscvt")
+
AARCH64_OPT_FMV_EXTENSION("fcma", FCMA, (SIMD), (), (), "fcma")
AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 250edb7d426d..f652869625a8 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -361,7 +361,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
#define TARGET_ARMV8_3 AARCH64_HAVE_ISA (V8_3A)
/* Javascript conversion instruction from Armv8.3-a. */
-#define TARGET_JSCVT (TARGET_FLOAT && TARGET_ARMV8_3)
+#define TARGET_JSCVT AARCH64_HAVE_ISA (JSCVT)
/* Armv8.3-a Complex number extension to AdvSIMD extensions. */
#define TARGET_COMPLEX AARCH64_HAVE_ISA (FCMA)
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index 5c3478d4ee82..985a18fba678 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -119,7 +119,7 @@ __revl (unsigned long __value)
}
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.3-a")
+#pragma GCC target ("+nothing+jscvt")
__extension__ extern __inline int32_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__jcvt (double __a)
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
index 1d90e9ec9d97..603ee48d584b 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
@@ -7,7 +7,7 @@ int main()
return 0;
}
-/* { dg-final { scan-assembler {\.arch
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
} } */
+/* { dg-final { scan-assembler {\.arch
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
} } */
/* Check that an Armv8-A core doesn't fall apart on extensions without midr
values. */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
index 17050a0b72c9..e0ba97fb6e9a 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
@@ -7,7 +7,7 @@ int main()
return 0;
}
-/* { dg-final { scan-assembler {\.arch
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n}
} } */
+/* { dg-final { scan-assembler {\.arch
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n}
} } */
/* Check that an Armv8-A core doesn't fall apart on extensions without midr
values and that it enables optional features. */
