https://gcc.gnu.org/g:6818c0420ed9047d42ef500b7173f82583f9c121
commit 6818c0420ed9047d42ef500b7173f82583f9c121
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Jan 3 03:23:54 2025 -0500
Revert changes
Diff:
---
gcc/config/rs6000/altivec.md | 35 +++-------------------
gcc/config/rs6000/predicates.md | 26 ----------------
gcc/config/rs6000/rs6000.h | 3 --
gcc/config/rs6000/rs6000.md | 6 +---
.../gcc.target/powerpc/vector-rotate-left.c | 34 ---------------------
5 files changed, 5 insertions(+), 99 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 013960438b04..7edc288a6565 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,39 +1982,12 @@
}
[(set_attr "type" "vecperm")])
-;; -mcpu=future adds a vector rotate left word variant. There is no vector
-;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-;; However for testing, allow other xvrl variants. In particular, XVRLD for
-;; the sha3 tests for multibuf/singlebuf.
(define_insn "altivec_vrl<VI_char>"
- [(set (match_operand:VI2 0 "register_operand" "=v,wa")
- (rotate:VI2 (match_operand:VI2 1 "register_operand" "v,wa")
- (match_operand:VI2 2 "register_operand" "v,wa")))]
+ [(set (match_operand:VI2 0 "register_operand" "=v")
+ (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
+ (match_operand:VI2 2 "register_operand" "v")))]
"<VI_unit>"
- "@
- vrl<VI_char> %0,%1,%2
- xvrl<VI_char> %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")
- (set_attr "isa" "*,xvrlw")])
-
-(define_insn "*altivec_vrl<VI_char>_immediate"
- [(set (match_operand:VI2 0 "register_operand" "=wa,wa,wa,wa")
- (rotate:VI2 (match_operand:VI2 1 "register_operand" "wa,wa,wa,wa")
- (match_operand:VI2 2 "vector_shift_immediate"
"j,wM,wE,wS")))]
- "TARGET_XVRLW && <VI_unit>"
-{
- rtx op2 = operands[2];
- int value = 256;
- int num_insns = -1;
-
- if (!xxspltib_constant_p (op2, <MODE>mode, &num_insns, &value))
- gcc_unreachable ();
-
- operands[3] = GEN_INT (value & 0xff);
- return "xvrl<VI_char>i %x0,%x1,%3";
-}
+ "vrl<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vrlq"
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 276812573977..6485ee3eeecc 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -728,32 +728,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR whose elements are all the
-;; same and the elements can be an immediate shift or rotate factor
-(define_predicate "vector_shift_immediate"
- (match_code "const_vector,vec_duplicate,const_int")
-{
- int value = 256;
- int num_insns = -1;
-
- if (zero_constant (op, mode) || all_ones_constant (op, mode))
- return true;
-
- if (!xxspltib_constant_p (op, mode, &num_insns, &value))
- return false;
-
- switch (mode)
- {
- case V16QImode: return IN_RANGE (value, 0, 7);
- case V8HImode: return IN_RANGE (value, 0, 15);
- case V4SImode: return IN_RANGE (value, 0, 31);
- case V2DImode: return IN_RANGE (value, 0, 63);
- default: break;
- }
-
- return false;
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 00f6ff2be636..ec08c96d0f67 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -575,9 +575,6 @@ extern int rs6000_vector_align[];
below. */
#define RS6000_FN_TARGET_INFO_HTM 1
-/* Whether we have XVRLW support. */
-#define TARGET_XVRLW TARGET_FUTURE
-
/* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e7927b88eaf8..3b876462ec32 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -369,7 +369,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,xxeval,xvrlw"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,xxeval"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -426,10 +426,6 @@
(match_test "TARGET_PREFIXED && TARGET_XXEVAL"))
(const_int 1)
- (and (eq_attr "isa" "xvrlw")
- (match_test "TARGET_XVRLW"))
- (const_int 1)
-
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
deleted file mode 100644
index 5a5f37755077..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
- Altivec registers is generated. */
-
-#include <altivec.h>
-
-typedef vector unsigned int v4si_t;
-
-v4si_t
-rotl_v4si_scalar (v4si_t x, unsigned long n)
-{
- __asm__ (" # %x0" : "+f" (x));
- return (x << n) | (x >> (32 - n)); /* xvrlw. */
-}
-
-v4si_t
-rotr_v4si_scalar (v4si_t x, unsigned long n)
-{
- __asm__ (" # %x0" : "+f" (x));
- return (x >> n) | (x << (32 - n)); /* xvrlw. */
-}
-
-v4si_t
-rotl_v4si_vector (v4si_t x, v4si_t y)
-{
- __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */
- return vec_rl (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */
