https://gcc.gnu.org/g:931d7ba9de76d06871f6c5bf57ccee8a94e9557c
commit r15-5622-g931d7ba9de76d06871f6c5bf57ccee8a94e9557c
Author: Pan Li <pan2...@intel.com>
Date: Thu Nov 21 14:30:44 2024 +0800
RISC-V: Refactor the testcases for vector SAT_SUB
This patch would like to refactor the testcases of vector SAT_SUB
after move to rvv/autovec/sat folder. Includes:
* Refine the include header files.
* Remove unnecessary optimization options.
* Adjust dg-final by any-opts and/or no-opts if the rtl dump changes
on different optimization options (like O2, O3).
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c:
Refactor the test case for include, unnecessary option and
target on opts.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c:
Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c | 11 ++++++++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c | 11 ++++++++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c | 2 +-
94 files changed, 153 insertions(+), 143 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c
index 5ed44d9fe707..0cb782ab1121 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_1(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c
index e67da174badb..375a06fa57fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_1(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c
index 0efdf6581812..4a011a66b06d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c
@@ -1,9 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_1(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { no-opts
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
+ } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
+ } } } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c
index b989cb6c1e1d..8de33735fb5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_1(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c
index becaa6b50407..3a6e3a5f00b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_10(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c
index e104793b9a71..f7618741cb41 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_10(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c
index c73b98e73a88..e510a536c9c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_10(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c
index aa90e04f33d5..12b1267cf5e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_10(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c
index cde246527117..3d456bfd4a9f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_2(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c
index 539951965860..4bad003868cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_2(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c
index ade479ec758b..cfe7eef5a0b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c
@@ -1,9 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_2(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { no-opts
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
+ } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
+ } } } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c
index 6c42573830c7..5be4e44b4596 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_2(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c
index b2fc9887b5a4..10b96921fc5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_3(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c
index 944b197f21f2..8714ca4daff1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_3(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c
index 862fd41176f0..a0e3caaf7cf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_3(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c
index 6221f18a1e71..b36e2f23e990 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_3(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c
index d3eadae0cb6b..9ae89f9a4d51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_4(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c
index b9f61fd02b17..870979013fa0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_4(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c
index 8171a3e9fcc9..b658fe6053eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_4(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c
index edadbf0d0468..602616b5e7db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_4(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c
index d259675c961b..d65f5b7c2202 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_5(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c
index 19aaa7e2a87e..fa65f9607a72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_5(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c
index ea95a372a557..c129df955d83 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_5(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c
index 4e1f65500e17..5dc1eed26a56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_5(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c
index de8defcc641e..b4cfdd35eaa6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_6(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c
index aed21c7bab78..7c45b782dc32 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_6(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c
index 8bfe35d82560..de7adf076aba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_6(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c
index 9fee79550467..ea20185d0978 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_6(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c
index 7994bbbcdc5a..b4b78f8a31b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_7(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c
index 2f2665dd2b87..76f454fc727b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_7(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c
index 0c181e1dd4d3..484ac4a1683a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_7(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c
index 7554929823f8..1e9ede2f7a4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_7(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c
index ca187271e85e..3b66539a1540 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_8(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c
index 203776e9d0d0..19daa9b42f1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_8(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c
index 6aed87903e15..2123ff6866a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_8(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c
index b1fd6f9dae49..70c515338055 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_8(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c
index eaa7b33d410d..461049d2e9b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_9(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c
index f885b2c2237e..c7295ad6a326 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_9(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c
index 4f5ab4190585..b325e21ac07a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_9(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c
index b5caadb3e4b1..dbd2421a927a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_9(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c
index 1288c619be0d..97e50406e603 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c
index f584c2dc3680..a5428c430107 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c
index e469cf2e98d8..bdb65d91c1fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c
index ea7a537f0ee0..3fe5fe33befb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c
index 3856cb0439b9..0f4129ca665f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c
index 5c4683ee8a0c..8b995eb3a16a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c
index 8436c6482c39..d12d9815e83e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c
index cabf501631b5..384ef3e98091 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c
index 8aac5656adfe..5cf08ac3ed63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c
index 4b88f778f212..85c84542e64b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c
index d4df48df111e..67d5ac5d8998 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c
index 1c0a6734b5e4..809f07fc6fc4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c
index 7a9d5d0c3731..57839a9cd98a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c
index a1e4be2746ed..ffb0dcc4d186 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c
index a55e1c489de3..396667790b56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c
index 248a8052b7c7..e795f62bfe2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c
index 50f9aeb55dd2..0eecf829686f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c
index 66b500849394..1d0d16b7408d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c
index 90c779851896..98fdfa24b31a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c
index 4bbf15ce99eb..18a887dd345e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c
index 9926a6f8498f..ce44c049c57e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c
index 3aef3cf2882c..36ae7b322c78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c
index 969421185091..7b40ffdbed33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c
index 92044005487b..3b0807febea5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c
index c4e933bca14b..e972078eca5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c
index 4930eb10dfa7..54e28487cac2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c
index 0b0f38f4534e..33f3be04deba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c
index 1d3f2ca165f3..13760387814f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c
index 4e49247fe415..83241ef6f994 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c
index ea4be4a151db..f20bb21e3b1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c
index f44fb7ac5119..4ad0afd3a6f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c
index 56decee10269..3b33b136d414 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c
index 66110a4cb363..b212550fed33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c
index bae4e85ba8b4..1fb707c3e807 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c
index d3924bf35cb6..da8c09c1eaa1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c
index ab3e9455e119..647607f29cfa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c
index dbfcd8bfc7f6..9bb0664aa874 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c
index 636ba08af9cd..f142b8b37fbf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c
index ccf40875d2e4..574b91a12f8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c
index 0f20e4680543..2c8ee4232d72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c
index b161ff0410fd..72a00c28f8ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint16_t, 70)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c
index 13c8cf5753e3..d415c3ed9516 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint32_t, 5)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c
index 5ed237b62622..79b5e5259b6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint64_t, 9)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c
index 52192d76d507..999574741c78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint8_t, 10)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c
index f304d82f7d6b..11fdbcb1ef4e 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c
index 283d37f34d45..df5ac7328497 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c
index 2512975abcfd..a883d688aab9 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c
index 19d3bb087da8..07753c05a0ff 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
index 32e828c5c744..bd5897aabc51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
index 72afd0872d2d..37440ee66a9d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
index 674206bea37c..06aa7eb173d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c
index 9652c92a9336..ec659a769620 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define OUT_T uint16_t
#define IN_T uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c
index d73cfa24a69a..5e15b898de0b 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define OUT_T uint32_t
#define IN_T uint64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c
index d85a78366a4e..8f04623ddf75 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define OUT_T uint8_t
#define IN_T uint16_t
