https://gcc.gnu.org/g:338121378003260ace30295f47e17b74aa5b7d17
commit r15-5504-g338121378003260ace30295f47e17b74aa5b7d17
Author: Richard Sandiford <richard.sandif...@arm.com>
Date: Wed Nov 20 13:27:39 2024 +0000
aarch64: Refactor SVE predicated-to-unpredicated splits
There are separate patterns for predicated FADD, FSUB, and FMUL.
Previously they each had their own in-built split to convert the
instruction to unpredicated form where appropriate. However, it's
more convenient for later patches if we use a single separate split
instead.
gcc/
* config/aarch64/iterators.md (SVE_COND_FP): New code attribute.
* config/aarch64/aarch64-sve.md: Use a single define_split to
handle the conversion of predicated FADD, FSUB, and FMUL into
unpredicated forms.
Diff:
---
gcc/config/aarch64/aarch64-sve.md | 47 +++++++++++++++++----------------------
gcc/config/aarch64/iterators.md | 6 +++++
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index 7a48f900fa52..64ff0a86cd48 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -5310,9 +5310,25 @@
;; - FSUB
;; -------------------------------------------------------------------------
+;; Split a predicated instruction whose predicate is unused into an
+;; unpredicated instruction.
+(define_split
+ [(set (match_operand:SVE_FULL_F 0 "register_operand")
+ (unspec:SVE_FULL_F
+ [(match_operand:<VPRED> 1 "register_operand")
+ (match_operand:SI 4 "aarch64_sve_gp_strictness")
+ (match_operand:SVE_FULL_F 2 "register_operand")
+ (match_operand:SVE_FULL_F 3 "register_operand")]
+ <SVE_COND_FP>))]
+ "TARGET_SVE
+ && reload_completed
+ && INTVAL (operands[4]) == SVE_RELAXED_GP"
+ [(set (match_dup 0)
+ (SVE_UNPRED_FP_BINARY:SVE_FULL_F (match_dup 2) (match_dup 3)))]
+)
+
;; Unpredicated floating-point binary operations (post-RA only).
-;; These are generated by splitting a predicated instruction whose
-;; predicate is unused.
+;; These are generated by the split above.
(define_insn "*post_ra_<sve_fp_op><mode>3"
[(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
(SVE_UNPRED_FP_BINARY:SVE_FULL_F
@@ -5678,7 +5694,7 @@
;; -------------------------------------------------------------------------
;; Predicated floating-point addition.
-(define_insn_and_split "@aarch64_pred_<optab><mode>"
+(define_insn "@aarch64_pred_<optab><mode>"
[(set (match_operand:SVE_FULL_F 0 "register_operand")
(unspec:SVE_FULL_F
[(match_operand:<VPRED> 1 "register_operand")
@@ -5696,13 +5712,6 @@
[ ?&w , Upl , w , vsN , i ; yes ] movprfx\t%0,
%2\;fsub\t%0.<Vetype>, %1/m, %0.<Vetype>, #%N3
[ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0,
%2\;fadd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
}
- ; Split the unpredicated form after reload, so that we don't have
- ; the unnecessary PTRUE.
- "&& reload_completed
- && register_operand (operands[3], <MODE>mode)
- && INTVAL (operands[4]) == SVE_RELAXED_GP"
- [(set (match_dup 0) (plus:SVE_FULL_F (match_dup 2) (match_dup 3)))]
- ""
)
;; Predicated floating-point addition of a constant, merging with the
@@ -6001,7 +6010,7 @@
;; -------------------------------------------------------------------------
;; Predicated floating-point subtraction.
-(define_insn_and_split "@aarch64_pred_<optab><mode>"
+(define_insn "@aarch64_pred_<optab><mode>"
[(set (match_operand:SVE_FULL_F 0 "register_operand")
(unspec:SVE_FULL_F
[(match_operand:<VPRED> 1 "register_operand")
@@ -6018,13 +6027,6 @@
[ ?&w , Upl , vsA , w , i ; yes ] movprfx\t%0,
%3\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2
[ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0,
%2\;fsub\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
}
- ; Split the unpredicated form after reload, so that we don't have
- ; the unnecessary PTRUE.
- "&& reload_completed
- && register_operand (operands[2], <MODE>mode)
- && INTVAL (operands[4]) == SVE_RELAXED_GP"
- [(set (match_dup 0) (minus:SVE_FULL_F (match_dup 2) (match_dup 3)))]
- ""
)
;; Predicated floating-point subtraction from a constant, merging with the
@@ -6430,7 +6432,7 @@
;; -------------------------------------------------------------------------
;; Predicated floating-point multiplication.
-(define_insn_and_split "@aarch64_pred_<optab><mode>"
+(define_insn "@aarch64_pred_<optab><mode>"
[(set (match_operand:SVE_FULL_F 0 "register_operand")
(unspec:SVE_FULL_F
[(match_operand:<VPRED> 1 "register_operand")
@@ -6446,13 +6448,6 @@
[ ?&w , Upl , w , vsM , i ; yes ] movprfx\t%0,
%2\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
[ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0,
%2\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
}
- ; Split the unpredicated form after reload, so that we don't have
- ; the unnecessary PTRUE.
- "&& reload_completed
- && register_operand (operands[3], <MODE>mode)
- && INTVAL (operands[4]) == SVE_RELAXED_GP"
- [(set (match_dup 0) (mult:SVE_FULL_F (match_dup 2) (match_dup 3)))]
- ""
)
;; Merging forms are handled through SVE_COND_FP_BINARY and
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index bded779de480..0137700d4890 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2971,6 +2971,12 @@
(define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec")
(plus "inc") (ss_plus "sqinc") (us_plus "uqinc")])
+;; The predicated FP operation associated with each rtl code. This is only
+;; useful for operations that have both predicated and unpredicated forms.
+(define_code_attr SVE_COND_FP [(plus "UNSPEC_COND_FADD")
+ (minus "UNSPEC_COND_FSUB")
+ (mult "UNSPEC_COND_FMUL")])
+
;; -------------------------------------------------------------------
;; Int Iterators.
;; -------------------------------------------------------------------
