https://gcc.gnu.org/g:fa18217f60f75c9cc045b3ebb43707917705d490
commit r15-5499-gfa18217f60f75c9cc045b3ebb43707917705d490
Author: Pan Li <pan2...@intel.com>
Date: Wed Nov 20 15:16:22 2024 +0800
RISC-V: Refine the rtl dump expand check for vector SAT_ADD
This patch would like to remove the unnecessary option for the
vector SAT_ADD testcases at first. And the different optimization
option like O2 and O3 will be passed to the test files for rtl
expand dump check. If there are different dump check times for
different optimization options, the target no-opts and/or any-opts
will be leveraged for the dg-final check.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Remove
the unnecessary option and refine the rtl IFN dump check.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c:
Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c | 7 +++---
.../riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c | 7 +++---
.../rvv/autovec/sat/vec_sat_s_add-run-1-s16.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-1-s32.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-1-s64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-2-s16.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-2-s32.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-2-s64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-3-s16.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-3-s32.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-3-s64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-4-s16.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-4-s32.c | 2 +-
.../rvv/autovec/sat/vec_sat_s_add-run-4-s64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c | 25 +++++++++++++++++++---
.../riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add-run-1-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-1-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-1-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-2-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-2-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-2-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-3-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-3-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-3-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-4-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-4-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-4-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-5-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-5-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-5-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-6-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-6-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-6-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-7-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-7-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-7-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-8-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-8-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add-run-8-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c | 4 ++--
.../rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c | 2 +-
.../rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c | 2 +-
.../sat/vec_sat_u_add_imm_reconcile-1-u16.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-1-u32.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-1-u64.c | 4 ++--
.../autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-2-u16.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-2-u32.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-2-u64.c | 4 ++--
.../autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-3-u16.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-3-u32.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-3-u64.c | 4 ++--
.../autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-4-u16.c | 4 ++--
.../sat/vec_sat_u_add_imm_reconcile-4-u32.c | 4 ++--
.../autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c | 4 ++--
143 files changed, 274 insertions(+), 239 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
index c10521c15eb1..6ef8ecbc1701 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
index b818878a7bad..46a4b6fdbd08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
index 8dbc7e81fbfd..43c0e6306249 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
index 60bb9ea0576c..cc2bd5c9a79c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
index a26d3943e27b..4c496300d8e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
index 4ef1351dd299..34d25f7a46dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
index 4879103c1358..28544471a994 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
index 8cf0d06efdb2..0bba22667e4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
index 5dfecdb17328..ccbe65a330e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
index ebf825e0dd8c..d1c67c8cbe0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
index 82b29a089f45..49ca8d6d26e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
index 242ebb28d3e5..3a2c887983ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
index 5542616c90ab..aa13604ca279 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
index 091bfd15edf3..2f47e5ba5498 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
index 715f0575813b..1a943d2404f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
index ec3f8aee434f..9ec120df69d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c
index 5b5c9d3ad93a..4dbe8a331f22 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c
index 47d232a299cf..0c43227a3462 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c
index 6ac43a7905df..b7b36ae1126d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c
index 0869df96758f..245d0eef922a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c
index 07dcc58dfda3..a86d9b521d40 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c
index 696d1fcfc53f..c04414becc9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c
index 5106c23a26f8..0f15d0e271ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c
index c9605cc928a3..f86833fdfa48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c
index 2f73271b771d..156d9922b43a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c
index bcb4d453955f..f514c7cb3981 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c
index 7c565706bfe7..d67d6dd7b7ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c
index 28c96dbcac9e..904fbad80534 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c
index 096d95b96f2c..e9dad063a245 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c
index a88cd3c0ffb1..9937e3692b18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c
index 74d547685a87..26895a7ddb79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c
index ccfbee1e8f59..07458997d617 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
index a7148c1228cb..88450517657b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
@@ -1,9 +1,28 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_1(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
+ "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1"
+ "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2"
+ "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m3"
+ "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4"
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m3"
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
+ } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target any-opts
+ "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1"
+ "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2"
+ "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m3"
+ "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4"
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m3"
+ "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
+ } } } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
index 8a55a01b02eb..c740c693c01e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_1(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
index 9ac3524c2c96..1cc577f6c8b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_1(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
index 4df3407eec24..ecbc27725c7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_1(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
index 586682293669..73a23fadf13b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_2(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
index 4b8b3c92b63f..b62f30133e1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_2(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
index 0f135392914e..8bb2fbc87a29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_2(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
index 536cade5753e..ffc4342be9be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_2(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
index d31325a00ce5..effb4d48e271 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
/*
** vec_sat_u_add_uint16_t_fmt_3:
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
index 9c84b0f3292a..1b64fc18a901 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_3(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
index 4e87e0e6e733..fdda300d6053 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_3(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
index 73afb203a838..35e98475895a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_3(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
index 0092492a535c..aaac0f0eb286 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_4(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
index e71758d9c4ea..6ad6904335cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_4(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
index f1ee836cb9ed..adb27bbf56c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_4(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
index 1320b05e76cb..4b337b3649b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_4(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
index e1f3b00736be..acfe5b558845 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_5(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
index 28744069474d..aba5b0449e8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_5(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
index 92167185035a..7d5d8cc99ebb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_5(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
index 0293055c3bb1..592c976019a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_5(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
index 1626e857d28f..1bd4cf5715dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_6(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
index 222d1ab68ce5..f358bf4b42af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_6(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
index 7a8843389e32..715974ef3a7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_6(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
index 8569956cd54c..055e44d64877 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_6(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
index f68c5bfd2c5b..e5b5d7e5902e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_7(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
index ef6bba3e4b07..be71df2aee7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_7(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
index cc60058799b5..442be2109bb9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_7(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
index b42031230aaf..a9f9c858c7f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_7(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
index 988d97a3428c..7ed1d1211fe5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_8(uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
index 9f702c68baae..6527af2d210d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_8(uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
index a90fe6a8c36a..971795cad082 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_8(uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
index 8792bb6112b9..99deffea15bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_8(uint8_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c
index c23214f19a75..bbe2f831d828 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c
index a61fc4ee5ad3..eb5a9da2c615 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c
index b11b984b1878..c39d9ccd5b26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c
index 0b5c1bc5e3ee..6cb1de9557aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c
index 6b58d79c2a1e..078dc3525e9d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c
index 714cbf0774d3..e84bba928bf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c
index cacf65efc10a..493c4e86db6d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c
index 5efe06c668b5..7939b4330d54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c
index 4239e93522f0..a3c16acbdac9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c
index ded6c2e9f053..b3135100b461 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c
index deadae6807e2..3dbc836632ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c
index 98d226aa7d25..0fc1999d5ee2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c
index 8b49e808b0f2..3af72b1bb4af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c
index 08d60569ad70..ffc5a2f4e6d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c
index 2039f6c65b33..39f37c3661c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c
index 2872072e26dd..36123cf57196 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c
index 5eb886d37e68..eb1b3c2e6e8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c
index 2077cde09d76..57513ede1143 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c
index af23da12f8d8..caf80bcdbc5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c
index 1dbece4ce81b..d9e53a815412 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c
index 7c6b6a024d6f..555b349fa51c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c
index 6d707e88d156..c3b11eea534d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c
index cf41743310c3..171e14699953 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c
index 606741af0c7e..0887f261f213 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c
index 949c2df63c19..caf1fe02b84e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c
index 0a7159ef9982..c1b7bc38aa31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c
index bd296e301401..8cc0de84dacb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c
index 8ac6eb46f141..a707a742d9f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c
index 29209174aeb9..9544a46039fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint16_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c
index 925896ab0ad6..5e38ebca6fd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint32_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c
index 56bc2ff8ce18..e27cae10783b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint64_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c
index 3998ffcbd12d..19236a9a4862 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#define T uint8_t
#define N 16
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
index 00ff60baa761..bd549f7882d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint16_t, 15)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
index 281ce2a1db55..75d5a67e1c85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint32_t, 33)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
index 391d2db32a35..2195dce98ef3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint64_t, 129)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
index ac2be7189130..f61df646c73d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
index e50b7b1e13f1..fa99826135cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint16_t, 15)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
index bc6d441759f3..a343104a6283 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint32_t, 33)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
index 870213eda390..ee8d8e675e3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint64_t, 129)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
index 54fcbd145a74..b35cdbe9207b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
index c6db8073bfa0..d8a7da79c5cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 15)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
index 517db1dc8c63..be4e263a956b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 33u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
index 318cafcb10cb..d29807a7981f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 129ull)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
index de5673943891..b190b28e3440 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
index 02c10fa4a26f..f528b95fd2c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint16_t, 15)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
index 4a93c7f89cbb..de6570bb32d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint32_t, 33u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
index e418d6b47ebc..f2aa70816b31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 129ull)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
index db6a28018496..a3045ad0a008 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint8_t, 9u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c
index 3a45cf16ed8e..dba87ac07203 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c
index 52723ed1dbf3..cf96f14b341d 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c
index 2c76ae216b3b..8ec1f1a40b12 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c
index b0d2799b1e0f..41524753a351 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c
index 8d6b90c6d4ba..9735a9ab144b 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c
index ef0d9fdca0fe..44f4ef38d5af 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c
index cb8bf7346181..4309eb4851b8 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c
index 9cc1eeda82e6..50037f5e4d10 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c
index a96fd757f159..7a4e6bedc0a0 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c
index bdfe5e8f7d66..ee998e0e35b0 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c
index bf89c358243e..8b982cb2f679 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c
index e218779829a8..b380eb08a1f8 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c
index c5fb4d16b526..00098a6d2ffa 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c
index e45beef7c38f..e070fe5e2cf7 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c
index f0a82f31d4fb..edf9a60aef3e 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint64_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c
index 612638c72762..7de36d21bd77 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
index f8033db77718..74793603bc2b 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 219)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
index ba48f4841423..38402a34aefe 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 299)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
index 1a41a6da1551..90b0bff92b71 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 301u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
index 7f6d612e89b1..2aaef2f66367 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
index c6c272754f9e..94a8e6715bd6 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 65530)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
index bd72b2471d4a..5c5dc25c72e0 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 65559)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
index 678aa9720777..5d99e79b6237 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 75559u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
index 9e9509de524e..02f07ff0cdc7 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 9u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
index 4ab4adee8003..8f18b82819f7 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967205u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
index d2b1e315fbf4..2ddecd8e0054 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967495ll)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
index b260d706f59c..222ec989b34c 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 9294967495ull)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
index 33811b22ea96..2f6da167c621 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 911u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
index e63cf23e80f5..7e2df06ebf4a 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551615ull)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
index e12a69d6d434..5ab4f162d846 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 9223372036854775807ull)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
index 61536cd684a1..64c112d222dc 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
@@ -1,8 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 119u)
