https://gcc.gnu.org/g:7c7da1036509a988b9ca3492eb856081132b14b2
commit r15-5485-g7c7da1036509a988b9ca3492eb856081132b14b2
Author: Pan Li <pan2...@intel.com>
Date: Tue Nov 19 15:27:39 2024 +0800
RISC-V: Refine the rtl expand check for strided ld/st
This patch would like to remove the unnecessary option for the
strided load/store testcases. After fix the option from the rvv.exp,
both the O2 and O3 will be passed to the test files for rtl expand
dump check but the O2 has 2 time for IFN while the O3 has 4 times with
-fvectorize specificed.
Thus, add xfail O2 for IFN 4 times check, as well as xfail O3 for 2
times check.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Remove
unnecessary optimization option and xfail O2/O3 diff IFN times
from the rtl expand dump.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c | 8 +++++---
11 files changed, 55 insertions(+), 33 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
index 41fe2b20a980..c409c5724b1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(_Float16)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
index 650b5fce4e8f..01e27d62276f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(float)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
index c0559a9265ec..0b4ec20a1825 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(double)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
index 641eaf149774..10875bd5bdec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(int16_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
index 5fc1ea91c5bf..bb3ff40ac06b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(int32_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
index 1819941cc36b..e0b149fa57fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(int64_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
index 119a6d75fba9..9dda4b4af516 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(int8_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse8.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse8.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
index 19d4f6edc877..c13e0dc5bc7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
index 10b1d4fefb5d..2c6c45961e8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
index b1654b8c80fa..5e817e832e1d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
index 273dcb83b0b0..9092aa713270 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
@@ -1,11 +1,13 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model
-fdump-rtl-expand-details" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } }
*/
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
xfail { any-opts "-O2" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
xfail { any-opts "-O3" } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
xfail { any-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vlse8.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse8.v} 1 } } */
