https://gcc.gnu.org/g:4981d1eb6364a7973fe0b8255851bb433759b263
commit 4981d1eb6364a7973fe0b8255851bb433759b263
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Sat Nov 16 02:15:46 2024 -0500
Revert changes
Diff:
---
gcc/config/rs6000/altivec.md | 35 +-
gcc/config/rs6000/fusion.md | 660 ++++++++++++++--------------------
gcc/config/rs6000/genfusion.pl | 102 +-----
gcc/config/rs6000/predicates.md | 40 +--
gcc/config/rs6000/rs6000.cc | 3 -
gcc/config/rs6000/rs6000.h | 3 -
gcc/config/rs6000/rs6000.md | 11 +-
gcc/config/rs6000/rs6000.opt | 4 -
gcc/testsuite/lib/target-supports.exp | 35 --
9 files changed, 274 insertions(+), 619 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index d4ee50322ca1..00dad4b91f1c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1983,39 +1983,12 @@
}
[(set_attr "type" "vecperm")])
-;; -mcpu=future adds a vector rotate left word variant. There is no vector
-;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-;; However for testing, allow other xvrl variants. In particular, XVRLD for
-;; the sha3 tests for multibuf/singlebuf.
(define_insn "altivec_vrl<VI_char>"
- [(set (match_operand:VI2 0 "register_operand" "=v,wa")
- (rotate:VI2 (match_operand:VI2 1 "register_operand" "v,wa")
- (match_operand:VI2 2 "register_operand" "v,wa")))]
+ [(set (match_operand:VI2 0 "register_operand" "=v")
+ (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
+ (match_operand:VI2 2 "register_operand" "v")))]
"<VI_unit>"
- "@
- vrl<VI_char> %0,%1,%2
- xvrl<VI_char> %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")
- (set_attr "isa" "*,xvrlw")])
-
-(define_insn "*altivec_vrl<VI_char>_immediate"
- [(set (match_operand:VI2 0 "register_operand" "=wa,wa,wa,wa")
- (rotate:VI2 (match_operand:VI2 1 "register_operand" "wa,wa,wa,wa")
- (match_operand:VI2 2 "vector_shift_immediate"
"j,wM,wE,wS")))]
- "TARGET_XVRLW && <VI_unit>"
-{
- rtx op2 = operands[2];
- int value = 256;
- int num_insns = -1;
-
- if (!xxspltib_constant_p (op2, <MODE>mode, &num_insns, &value))
- gcc_unreachable ();
-
- operands[3] = GEN_INT (value & 0xff);
- return "xvrl<VI_char>i %x0,%x1,%3";
-}
+ "vrl<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vrlq"
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 215a3aae074f..4ed9ae1d69f4 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -1871,170 +1871,146 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vand
(define_insn "*fuse_vand_vand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"%v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"%v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vand %3,%3,%2
vand %3,%1,%0\;vand %3,%3,%2
vand %3,%1,%0\;vand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,1
vand %4,%1,%0\;vand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vand
(define_insn "*fuse_vandc_vand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vand %3,%3,%2
vandc %3,%1,%0\;vand %3,%3,%2
vandc %3,%1,%0\;vand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,2
vandc %4,%1,%0\;vand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vand
(define_insn "*fuse_veqv_vand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vand %3,%3,%2
veqv %3,%1,%0\;vand %3,%3,%2
veqv %3,%1,%0\;vand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,9
veqv %4,%1,%0\;vand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vand
(define_insn "*fuse_vnand_vand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vand %3,%3,%2
vnand %3,%1,%0\;vand %3,%3,%2
vnand %3,%1,%0\;vand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,14
vnand %4,%1,%0\;vand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vand
(define_insn "*fuse_vnor_vand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vand %3,%3,%2
vnor %3,%1,%0\;vand %3,%3,%2
vnor %3,%1,%0\;vand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,8
vnor %4,%1,%0\;vand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vand
(define_insn "*fuse_vor_vand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vand %3,%3,%2
vor %3,%1,%0\;vand %3,%3,%2
vor %3,%1,%0\;vand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,7
vor %4,%1,%0\;vand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vand
(define_insn "*fuse_vorc_vand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vand %3,%3,%2
vorc %3,%1,%0\;vand %3,%3,%2
vorc %3,%1,%0\;vand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,11
vorc %4,%1,%0\;vand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vand
(define_insn "*fuse_vxor_vand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vand %3,%3,%2
vxor %3,%1,%0\;vand %3,%3,%2
vxor %3,%1,%0\;vand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,6
vxor %4,%1,%0\;vand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vandc
@@ -2057,23 +2033,20 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vandc
(define_insn "*fuse_vandc_vandc"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vandc %3,%3,%2
vandc %3,%1,%0\;vandc %3,%3,%2
vandc %3,%1,%0\;vandc %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,13
vandc %4,%1,%0\;vandc %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vandc
@@ -2204,23 +2177,20 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> veqv
(define_insn "*fuse_vandc_veqv"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %3,%1,%0\;veqv %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,210
vandc %4,%1,%0\;veqv %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> veqv
@@ -2297,23 +2267,20 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> veqv
(define_insn "*fuse_vorc_veqv"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %3,%1,%0\;veqv %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,75
vorc %4,%1,%0\;veqv %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> veqv
@@ -2336,506 +2303,434 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vnand
(define_insn "*fuse_vand_vnand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vnand %3,%3,%2
vand %3,%1,%0\;vnand %3,%3,%2
vand %3,%1,%0\;vnand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,254
vand %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vnand
(define_insn "*fuse_vandc_vnand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vnand %3,%3,%2
vandc %3,%1,%0\;vnand %3,%3,%2
vandc %3,%1,%0\;vnand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,253
vandc %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vnand
(define_insn "*fuse_veqv_vnand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %3,%1,%0\;vnand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,246
veqv %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vnand
(define_insn "*fuse_vnand_vnand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vnand %3,%3,%2
vnand %3,%1,%0\;vnand %3,%3,%2
vnand %3,%1,%0\;vnand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,241
vnand %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vnand
(define_insn "*fuse_vnor_vnand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %3,%1,%0\;vnand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,247
vnor %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vnand
(define_insn "*fuse_vor_vnand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vnand %3,%3,%2
vor %3,%1,%0\;vnand %3,%3,%2
vor %3,%1,%0\;vnand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,248
vor %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vnand
(define_insn "*fuse_vorc_vnand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vnand %3,%3,%2
vorc %3,%1,%0\;vnand %3,%3,%2
vorc %3,%1,%0\;vnand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,244
vorc %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vnand
(define_insn "*fuse_vxor_vnand"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vnand %3,%3,%2
vxor %3,%1,%0\;vnand %3,%3,%2
vxor %3,%1,%0\;vnand %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,249
vxor %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vnor
(define_insn "*fuse_vand_vnor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vnor %3,%3,%2
vand %3,%1,%0\;vnor %3,%3,%2
vand %3,%1,%0\;vnor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,224
vand %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vnor
(define_insn "*fuse_vandc_vnor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vnor %3,%3,%2
vandc %3,%1,%0\;vnor %3,%3,%2
vandc %3,%1,%0\;vnor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,208
vandc %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vnor
(define_insn "*fuse_veqv_vnor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vnor %3,%3,%2
veqv %3,%1,%0\;vnor %3,%3,%2
veqv %3,%1,%0\;vnor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,96
veqv %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vnor
(define_insn "*fuse_vnand_vnor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %3,%1,%0\;vnor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,16
vnand %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vnor
(define_insn "*fuse_vnor_vnor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vnor %3,%3,%2
vnor %3,%1,%0\;vnor %3,%3,%2
vnor %3,%1,%0\;vnor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,112
vnor %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vnor
(define_insn "*fuse_vor_vnor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vnor %3,%3,%2
vor %3,%1,%0\;vnor %3,%3,%2
vor %3,%1,%0\;vnor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,128
vor %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vnor
(define_insn "*fuse_vorc_vnor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %3,%1,%0\;vnor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,64
vorc %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vnor
(define_insn "*fuse_vxor_vnor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vnor %3,%3,%2
vxor %3,%1,%0\;vnor %3,%3,%2
vxor %3,%1,%0\;vnor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,144
vxor %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vor
(define_insn "*fuse_vand_vor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vor %3,%3,%2
vand %3,%1,%0\;vor %3,%3,%2
vand %3,%1,%0\;vor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,31
vand %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vor
(define_insn "*fuse_vandc_vor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vor %3,%3,%2
vandc %3,%1,%0\;vor %3,%3,%2
vandc %3,%1,%0\;vor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,47
vandc %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vor
(define_insn "*fuse_veqv_vor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vor %3,%3,%2
veqv %3,%1,%0\;vor %3,%3,%2
veqv %3,%1,%0\;vor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,159
veqv %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vor
(define_insn "*fuse_vnand_vor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vor %3,%3,%2
vnand %3,%1,%0\;vor %3,%3,%2
vnand %3,%1,%0\;vor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,239
vnand %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vor
(define_insn "*fuse_vnor_vor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vor %3,%3,%2
vnor %3,%1,%0\;vor %3,%3,%2
vnor %3,%1,%0\;vor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,143
vnor %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vor
(define_insn "*fuse_vor_vor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"%v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"%v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vor %3,%3,%2
vor %3,%1,%0\;vor %3,%3,%2
vor %3,%1,%0\;vor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,127
vor %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vor
(define_insn "*fuse_vorc_vor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vor %3,%3,%2
vorc %3,%1,%0\;vor %3,%3,%2
vorc %3,%1,%0\;vor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,191
vorc %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vor
(define_insn "*fuse_vxor_vor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vor %3,%3,%2
vxor %3,%1,%0\;vor %3,%3,%2
vxor %3,%1,%0\;vor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,111
vxor %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vorc
@@ -2948,23 +2843,20 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vorc
(define_insn "*fuse_vorc_vorc"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %3,%1,%0\;vorc %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,79
vorc %4,%1,%0\;vorc %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vorc
@@ -2987,170 +2879,146 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vxor
(define_insn "*fuse_vand_vxor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (xor:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vxor %3,%3,%2
vand %3,%1,%0\;vxor %3,%3,%2
vand %3,%1,%0\;vxor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,30
vand %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vxor
(define_insn "*fuse_vandc_vxor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,45
vandc %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vxor
(define_insn "*fuse_veqv_vxor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (xor:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vxor %3,%3,%2
veqv %3,%1,%0\;vxor %3,%3,%2
veqv %3,%1,%0\;vxor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,150
veqv %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vxor
(define_insn "*fuse_vnand_vxor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vxor %3,%3,%2
vnand %3,%1,%0\;vxor %3,%3,%2
vnand %3,%1,%0\;vxor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,225
vnand %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vxor
(define_insn "*fuse_vnor_vxor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v")))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vxor %3,%3,%2
vnor %3,%1,%0\;vxor %3,%3,%2
vnor %3,%1,%0\;vxor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,135
vnor %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vxor
(define_insn "*fuse_vor_vxor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (xor:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vxor %3,%3,%2
vor %3,%1,%0\;vxor %3,%3,%2
vor %3,%1,%0\;vxor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,120
vor %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vxor
(define_insn "*fuse_vorc_vxor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vxor %3,%3,%2
vorc %3,%1,%0\;vxor %3,%3,%2
vorc %3,%1,%0\;vxor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,180
vorc %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vxor
(define_insn "*fuse_vxor_vxor"
- [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
- (xor:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,wa,v")
- (match_operand:VM 1 "vector_fusion_operand"
"%v,v,v,wa,v"))
- (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
+ [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
+ (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
+ (match_operand:VM 1 "altivec_register_operand"
"%v,v,v,v"))
+ (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %3,%1,%0\;vxor %3,%3,%2
- xxeval %x3,%x2,%x1,%x0,105
vxor %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
+ (set_attr "length" "8")])
;; add-add fusion pattern generated by gen_addadd
(define_insn "*fuse_add_add"
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index de1590741a67..2271be14bfa4 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -211,76 +211,25 @@ sub gen_logical_addsubf
$inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4,
$bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp,
$ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,$outer_name,
- $fuse_type, $xxeval, $c5, $vect_pred, $vect_inner_arg0,
$vect_inner_arg1,
- $vect_inner_exp, $vect_outer_arg2, $vect_outer_exp);
-
- my %xxeval_fusions = (
- "vand_vand" => 1,
- "vandc_vand" => 2,
- "vxor_vand" => 6,
- "vor_vand" => 7,
- "vnor_vand" => 8,
- "veqv_vand" => 9,
- "vorc_vand" => 11,
- "vandc_vandc" => 13,
- "vnand_vand" => 14,
- "vnand_vnor" => 16,
- "vand_vxor" => 30,
- "vand_vor" => 31,
- "vandc_vxor" => 45,
- "vandc_vor" => 47,
- "vorc_vnor" => 64,
- "vorc_veqv" => 75,
- "vorc_vorc" => 79,
- "veqv_vnor" => 96,
- "vxor_vxor" => 105,
- "vxor_vor" => 111,
- "vnor_vnor" => 112,
- "vor_vxor" => 120,
- "vor_vor" => 127,
- "vor_vnor" => 128,
- "vnor_vxor" => 135,
- "vnor_vor" => 143,
- "vxor_vnor" => 144,
- "veqv_vxor" => 150,
- "veqv_vor" => 159,
- "vorc_vxor" => 180,
- "vorc_vor" => 191,
- "vandc_vnor" => 208,
- "vandc_veqv" => 210,
- "vand_vnor" => 224,
- "vnand_vxor" => 225,
- "vnand_vor" => 239,
- "vnand_vnand" => 241,
- "vorc_vnand" => 244,
- "veqv_vnand" => 246,
- "vnor_vnand" => 247,
- "vor_vnand" => 248,
- "vxor_vnand" => 249,
- "vandc_vnand" => 253,
- "vand_vnand" => 254,
- );
-
- KIND: foreach $kind ('scalar','vector') {
+ $fuse_type);
+ KIND: foreach $kind ('scalar','vector') {
@outer_ops = @logicals;
if ( $kind eq 'vector' ) {
$vchr = "v";
$mode = "VM";
$pred = "altivec_register_operand";
- $vect_pred = "vector_fusion_operand";
$constraint = "v";
$fuse_type = "fused_vector";
} else {
$vchr = "";
$mode = "GPR";
- $vect_pred = $pred = "gpc_reg_operand";
+ $pred = "gpc_reg_operand";
$constraint = "r";
$fuse_type = "fused_arith_logical";
push (@outer_ops, @addsub);
push (@outer_ops, ( "rsubf" ));
}
$c4 = "${constraint},${constraint},${constraint},${constraint}";
- $c5 = "${constraint},${constraint},${constraint},wa,${constraint}";
OUTER: foreach $outer ( @outer_ops ) {
$outer_name = "${vchr}${outer}";
$is_subf = ( $outer eq "subf" );
@@ -308,40 +257,29 @@ sub gen_logical_addsubf
$inner_inv = $invert{$inner};
$inner_rtl = $rtlop{$inner};
$inner_op = "${vchr}${inner}";
-
# If both ops commute then we can specify % on operand 1
# so the pattern will let operands 1 and 2 interchange.
$both_commute = ($inner eq $outer) && ($commute2{$inner} == 1);
$bc = ""; if ( $both_commute ) { $bc = "%"; }
$inner_arg0 = "(match_operand:${mode} 0 \"${pred}\" \"${c4}\")";
$inner_arg1 = "(match_operand:${mode} 1 \"${pred}\" \"${bc}${c4}\")";
- $vect_inner_arg0 = "(match_operand:${mode} 0 \"${vect_pred}\"
\"${c5}\")";
- $vect_inner_arg1 = "(match_operand:${mode} 1 \"${vect_pred}\"
\"${bc}${c5}\")";
if ( ($inner_comp & 1) == 1 ) {
$inner_arg0 = "(not:${mode} $inner_arg0)";
- $vect_inner_arg0 = "(not:${mode} $vect_inner_arg0)";
}
if ( ($inner_comp & 2) == 2 ) {
$inner_arg1 = "(not:${mode} $inner_arg1)";
- $vect_inner_arg1 = "(not:${mode} $vect_inner_arg1)";
}
$inner_exp = "(${inner_rtl}:${mode} ${inner_arg0}
${inner_arg1})";
- $vect_inner_exp = "(${inner_rtl}:${mode} ${vect_inner_arg0}
- ${vect_inner_arg1})";
if ( $inner_inv == 1 ) {
$inner_exp = "(not:${mode} $inner_exp)";
- $vect_inner_exp = "(not:${mode} $vect_inner_exp)";
}
$outer_arg2 = "(match_operand:${mode} 2 \"${pred}\" \"${c4}\")";
- $vect_outer_arg2 = "(match_operand:${mode} 2 \"${vect_pred}\"
\"${c5}\")";
if ( ($outer_comp & 1) == 1 ) {
$outer_arg2 = "(not:${mode} $outer_arg2)";
- $vect_outer_arg2 = "(not:${mode} $vect_outer_arg2)";
}
if ( ($outer_comp & 2) == 2 ) {
$inner_exp = "(not:${mode} $inner_exp)";
- $vect_inner_exp = "(not:${mode} $vect_inner_exp)";
}
if ( $is_subf ) {
$outer_32 = "%2,%3";
@@ -353,23 +291,15 @@ sub gen_logical_addsubf
if ( $is_rsubf == 1 ) {
$outer_exp = "(${outer_rtl}:${mode} ${outer_arg2}
${inner_exp})";
- $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_outer_arg2}
- ${vect_inner_exp})";
} else {
$outer_exp = "(${outer_rtl}:${mode} ${inner_exp}
${outer_arg2})";
- $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_inner_exp}
- ${vect_outer_arg2})";
}
if ( $outer_inv == 1 ) {
$outer_exp = "(not:${mode} $outer_exp)";
- $vect_outer_exp = "(not:${mode} $vect_outer_exp)";
}
- # See if we can use xxeval on vector fusion
- $xxeval = $xxeval_fusions{"${inner_op}_${outer_name}"};
- if (!$xxeval) {
- $insn = <<"EOF";
+ $insn = <<"EOF";
;; $ftype fusion pattern generated by gen_logical_addsubf
;; $kind $inner_op -> $outer_name
@@ -388,30 +318,6 @@ sub gen_logical_addsubf
(set_attr "length" "8")])
EOF
- } else {
- $insn = <<"EOF";
-
-;; $ftype fusion pattern generated by gen_logical_addsubf
-;; $kind $inner_op -> $outer_name
-(define_insn "*fuse_${inner_op}_${outer_name}"
- [(set (match_operand:${mode} 3 "${vect_pred}"
"=&0,&1,&${constraint},wa,${constraint}")
- ${vect_outer_exp})
- (clobber (match_scratch:${mode} 4 "=X,X,X,X,&${constraint}"))]
- "(TARGET_P10_FUSION)"
- "@
- ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
- ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
- ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
- xxeval %x3,%x2,%x1,%x0,${xxeval}
- ${inner_op} %4,%1,%0\\;${outer_op} %3,${outer_42}"
- [(set_attr "type" "$fuse_type")
- (set_attr "cost" "6")
- (set_attr "length" "8")
- (set_attr "prefixed" "*,*,*,yes,*")
- (set_attr "isa" "*,*,*,xxeval,*")])
-EOF
- }
-
print $insn;
}
}
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index fccfbd7e4904..0b78901e94be 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -82,7 +82,7 @@
return ALTIVEC_REGNO_P (REGNO (op));
})
-;; Return 1 if op is a VSX register
+;; Return 1 if op is a VSX register.
(define_predicate "vsx_register_operand"
(match_operand 0 "register_operand")
{
@@ -119,18 +119,6 @@
return VSX_REGNO_P (REGNO (op));
})
-;; Return 1 if op is a register that can be used for vector fusion. If XXEVAL
-;; is supported, return true for all VSX registers, otherwise the fusion is
-;; limited to Altivec registers since the machine only fuses Altivec
-;; operations.
-(define_predicate "vector_fusion_operand"
- (match_operand 0 "register_operand")
-{
- return (TARGET_XXEVAL && TARGET_PREFIXED
- ? vsx_register_operand (op, mode)
- : altivec_register_operand (op, mode));
-})
-
;; Return 1 if op is a vector register that operates on floating point vectors
;; (either altivec or VSX).
(define_predicate "vfloat_operand"
@@ -728,32 +716,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR whose elements are all the
-;; same and the elements can be an immediate shift or rotate factor
-(define_predicate "vector_shift_immediate"
- (match_code "const_vector,vec_duplicate,const_int")
-{
- int value = 256;
- int num_insns = -1;
-
- if (zero_constant (op, mode) || all_ones_constant (op, mode))
- return true;
-
- if (!xxspltib_constant_p (op, mode, &num_insns, &value))
- return false;
-
- switch (mode)
- {
- case V16QImode: return IN_RANGE (value, 0, 7);
- case V8HImode: return IN_RANGE (value, 0, 15);
- case V4SImode: return IN_RANGE (value, 0, 31);
- case V2DImode: return IN_RANGE (value, 0, 63);
- default: break;
- }
-
- return false;
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index bdaa6973e704..dc5b7eb74d4b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -24721,9 +24721,6 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
{ "speculate-indirect-jumps",
offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
- { "xxeval",
- offsetof (struct gcc_options, x_TARGET_XXEVAL),
- offsetof (struct cl_target_option, x_TARGET_XXEVAL), },
};
/* Inner function to handle attribute((target("..."))) and #pragma GCC target
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 576c7ae66bb4..f95318dd5536 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -578,9 +578,6 @@ extern int rs6000_vector_align[];
below. */
#define RS6000_FN_TARGET_INFO_HTM 1
-/* Whether we have XVRLW support. */
-#define TARGET_XVRLW TARGET_FUTURE
-
/* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 62b45a6bd613..d266f93ff2e4 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -369,7 +369,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,xxeval,xvrlw"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -421,15 +421,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "xxeval")
- (match_test "TARGET_PREFIXED && TARGET_XXEVAL"))
- (const_int 1)
-
- (and (eq_attr "isa" "xvrlw")
- (match_test "TARGET_XVRLW"))
- (const_int 1)
-
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index cfd81a177a6e..0d71dbaf2fc1 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -631,10 +631,6 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
-mxxeval
-Target Undocumented Var(TARGET_XXEVAL) Init(1) Save
-Generate (do not generate) code that uses the XXEVAL instruction.
-
; Documented parameters
-param=rs6000-vect-unroll-limit=
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index e2504886d86b..fd58682cae3b 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7402,41 +7402,6 @@ proc check_effective_target_power10_ok { } {
}
}
-# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
-# some potential new instructions.
-proc check_effective_target_powerpc_future_ok { } {
- return [check_no_compiler_messages powerpc_future_ok object {
- #ifndef _ARCH_PWR_FUTURE
- #error "-mcpu=future is not supported"
- #else
- int dummy;
- #endif
- } "-mcpu=future"]
-}
-
-# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
-# the dense math operations.
-proc check_effective_target_powerpc_dense_math_ok { } {
- if { ([istarget powerpc*-*-*]) } {
- return [check_no_compiler_messages powerpc_dense_math_ok object {
- __vector_quad vq;
- int main (void) {
- #ifndef __DENSE_MATH__
- #error "target does not have dense math support."
- #else
- /* Make sure we have dense math support. */
- __vector_quad dmr;
- __asm__ ("dmsetaccz %A0" : "=wD" (dmr));
- vq = dmr;
- #endif
- return 0;
- }
- } "-mcpu=future"]
- } else {
- return 0;
- }
-}
-
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
