https://gcc.gnu.org/g:0f20f7746c0059c6a9a7b20c5f53783d503dcdd8
commit 0f20f7746c0059c6a9a7b20c5f53783d503dcdd8
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Nov 15 10:41:35 2024 -0500
Do not allow -mvsx to boost processor to power7.
This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7. The user must now use -mcpu=power7 or
higher.
This means if the user does -mvsx and the default processor does not have
VSX
support, it will be an error.
I have built both big endian and little endian bootstrap compilers and there
were no regressions.
I updated the 2 tests that used -mvsx to raise the cpu to power7, and the
test
case that checks if -mno-vsx produces the expected warning.
Can I install this patch on the GCC 15 trunk?
2024-11-15 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Check
if
the user asked for VSX instructions whether the cpu was at least
power7.
gcc/testsuite/
* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add
cpu=power7
when we need to add VSX support. Add test for adding cpu=power7
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 in target
__attribute__
when requesting VSX instructions.
* gcc.target/powerpc/pr87496-1.c: Update options to use
-mdejagnu-cpu=power6 to get the appropriate error message.
Diff:
---
gcc/config/rs6000/rs6000.cc | 7 +++++
gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 38 +++++++++++++++++++------
gcc/testsuite/gcc.target/powerpc/pr115688.c | 3 +-
gcc/testsuite/gcc.target/powerpc/pr87496-1.c | 2 +-
4 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2b185165610f..6b1a973c2487 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3860,6 +3860,13 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_VSX;
rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
}
+ else if (!TARGET_POWER7)
+ {
+ if (explicit_vsx_p)
+ error ("%<-mvsx%> requires at least %<-mcpu=power%>");
+ rs6000_isa_flags &= ~OPTION_MASK_VSX;
+ rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
+ }
}
/* If hard-float/altivec/vsx were explicitly turned off then don't allow
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index feef76db4618..5e2ecf34f249 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_fprs } */
/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
/* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
/* { dg-final { scan-assembler-times "fadds" 1 } } */
@@ -18,10 +18,6 @@
#error "__VSX__ should not be defined."
#endif
-#pragma GCC target("altivec,vsx")
-#include <altivec.h>
-#pragma GCC reset_options
-
#pragma GCC push_options
#pragma GCC target("altivec,no-vsx")
@@ -33,6 +29,7 @@
#error "__VSX__ should not be defined."
#endif
+/* Altivec build, generate vaddfp. */
void
av_add (vector float *a, vector float *b, vector float *c)
{
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
unsigned long n = SIZE / 4;
for (i = 0; i < n; i++)
- a[i] = vec_add (b[i], c[i]);
+ a[i] = b[i] + c[i];
}
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX. */
+#pragma GCC target("cpu=power7,vsx")
#ifndef __ALTIVEC__
#error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
#error "__VSX__ should be defined."
#endif
+/* VSX build on power7, generate xsaddsp. */
void
vsx_add (vector float *a, vector float *b, vector float *c)
{
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
unsigned long n = SIZE / 4;
for (i = 0; i < n; i++)
- a[i] = vec_add (b[i], c[i]);
+ a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp. */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+ unsigned long i;
+ unsigned long n = SIZE / 4;
+
+ for (i = 0; i < n; i++)
+ a[i] = b[i] + c[i];
}
#pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
#ifdef __ALTIVEC__
#error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
#error "__VSX__ should not be defined."
#endif
+/* Default power5 build, generate scalar fadds. */
void
norm_add (float *a, float *b, float *c)
{
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
/* Verify there is no ICE under 32 bit env. */
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX. */
+__attribute__((target("cpu=power7,vsx")))
int test (void)
{
return 0;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr87496-1.c
b/gcc/testsuite/gcc.target/powerpc/pr87496-1.c
index b8d00286256a..2029ecacaf9b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr87496-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr87496-1.c
@@ -2,7 +2,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target longdouble128 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power7 -mabi=ieeelongdouble -mno-popcntd
-Wno-psabi" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power6 -mabi=ieeelongdouble -Wno-psabi" } */
int i;
