https://gcc.gnu.org/g:cd71abc54f8d44ac9f63dd832554d7c8d95706c6
commit cd71abc54f8d44ac9f63dd832554d7c8d95706c6
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Nov 14 14:25:45 2024 -0500
Change TARGET_POPCNTD to TARGET_POWER7.
This patch changes TARGET_POPCNTD to TARGET_POWER7 and OPTION_MASK_POPCNTD
to
OPTION_MASK_POWER7. The -mpopcntd switch is not being changed, just the
name of
the macros used to determine if the PowerPC processor supports ISA 2.6
(Power7).
2024-11-14 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* gcc/config/rs6000/dfp.md (cmp<mode>_internal1): Change
TARGET_POPCNTD
to TARGET_POWER7. Change OPTION_MASK_POPCNTD to OPTION_MASK_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros):
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_EMBEDDED):
Likewise.
(ISA_2_6_MASKS_SERVER): Likewise.
(POWERPC_MASKS): Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare):
Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz<mode>2): Likewise.
(ffs<mode>2): Likewise.
(popcntb<mode>2): Likewise.
(lrint<mode>si): Likewise.
(lrint<mode>si): Likewise.
(lrint<mode>si_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_<mode>): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div<div_extend>_<mode>): Likewise.
* gcc/config/rs6000/rs6000.opt (-mpopcntd): Likewise.
Diff:
---
gcc/config/rs6000/dfp.md | 2 +-
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000-c.cc | 2 +-
gcc/config/rs6000/rs6000-cpus.def | 6 +++---
gcc/config/rs6000/rs6000-string.cc | 2 +-
gcc/config/rs6000/rs6000.cc | 18 +++++++++---------
gcc/config/rs6000/rs6000.h | 20 ++++++++++----------
gcc/config/rs6000/rs6000.md | 26 +++++++++++++-------------
gcc/config/rs6000/rs6000.opt | 6 ++++--
9 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd3..b8189390d410 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_DFP && TARGET_POPCNTD"
+ "TARGET_DFP && TARGET_POWER7"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..dae43b672ea7 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P6_64:
return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
- return TARGET_POPCNTD;
+ return TARGET_POWER7;
case ENB_P7_64:
- return TARGET_POPCNTD && TARGET_POWERPC64;
+ return TARGET_POWER7 && TARGET_POWERPC64;
case ENB_P8:
return TARGET_POWER8;
case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index b721c9925e19..5bdd6a45db6a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -428,7 +428,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
if ((flags & OPTION_MASK_POWER6) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
- if ((flags & OPTION_MASK_POPCNTD) != 0)
+ if ((flags & OPTION_MASK_POWER7) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
if ((flags & OPTION_MASK_POWER8) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 77cc199073e3..01ab0c0d6b7c 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -37,9 +37,9 @@
/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
altivec is a win so enable it. */
-#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
+#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POWER7)
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
- | OPTION_MASK_POPCNTD \
+ | OPTION_MASK_POWER7 \
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_VSX)
@@ -144,7 +144,7 @@
| OPTION_MASK_PCREL \
| OPTION_MASK_PCREL_OPT \
| OPTION_MASK_POWER5 \
- | OPTION_MASK_POPCNTD \
+ | OPTION_MASK_POWER7 \
| OPTION_MASK_POWERPC64 \
| OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_PPC_GPOPT \
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index de618da9b5dc..b633d80110d0 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1949,7 +1949,7 @@ bool
expand_block_compare (rtx operands[])
{
/* TARGET_POPCNTD is already guarded at expand cmpmemsi. */
- gcc_assert (TARGET_POPCNTD);
+ gcc_assert (TARGET_POWER7);
/* For P8, this case is complicated to handle because the subtract
with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 36129248299c..eae5937972ed 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -259,7 +259,7 @@ struct clone_map {
static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
{ 0, "" }, /* Default options. */
{ OPTION_MASK_POWER6, "arch_2_05" }, /* ISA 2.05 (power6).
*/
- { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
+ { OPTION_MASK_POWER7, "arch_2_06" }, /* ISA 2.06 (power7).
*/
{ OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
{ OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.0 (power9). */
{ OPTION_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */
@@ -1922,7 +1922,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -3916,7 +3916,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POPCNTD)
+ else if (TARGET_POWER7)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
@@ -4129,7 +4129,7 @@ rs6000_option_override_internal (bool global_init_p)
else if (TARGET_LONG_DOUBLE_128)
{
if (global_options.x_rs6000_ieeequad
- && (!TARGET_POPCNTD || !TARGET_VSX))
+ && (!TARGET_POWER7 || !TARGET_VSX))
error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT)
@@ -22431,7 +22431,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case POPCOUNT:
- *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
+ *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6);
return false;
case PARITY:
@@ -23208,8 +23208,8 @@ rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
return;
}
-/* Emit popcount intrinsic on TARGET_POWER5 and TARGET_POPCNTD (Power7)
- targets. DST is the target, and SRC is the argument operand. */
+/* Emit popcount intrinsic on TARGET_POWER5 and TARGET_POWER7 targets. DST is
+ the target, and SRC is the argument operand. */
void
rs6000_emit_popcount (rtx dst, rtx src)
@@ -23218,7 +23218,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
rtx tmp1, tmp2;
/* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
- if (TARGET_POPCNTD)
+ if (TARGET_POWER7)
{
if (mode == SImode)
emit_insn (gen_popcntdsi2 (dst, src));
@@ -24505,7 +24505,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "pcrel", OPTION_MASK_PCREL, false, true },
{ "pcrel-opt", OPTION_MASK_PCREL_OPT, false, true },
{ "popcntb", OPTION_MASK_POWER5, false, true },
- { "popcntd", OPTION_MASK_POPCNTD, false, true },
+ { "popcntd", OPTION_MASK_POWER7, false, true },
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 5b4cb9500a06..97f5d6bb8d9b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -442,7 +442,7 @@ extern int rs6000_vector_align[];
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
#define TARGET_IEEEQUAD rs6000_ieeequad
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
-#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
+#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
@@ -450,17 +450,17 @@ extern int rs6000_vector_align[];
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
|| TARGET_POWER6 /* ISA 2.05 */ \
- || TARGET_POPCNTD) /* ISA 2.06 */
+ || TARGET_POWER7) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
#define TARGET_LFIWAX TARGET_POWER6
-#define TARGET_LFIWZX TARGET_POPCNTD
-#define TARGET_FCFIDS TARGET_POPCNTD
-#define TARGET_FCFIDU TARGET_POPCNTD
-#define TARGET_FCFIDUS TARGET_POPCNTD
-#define TARGET_FCTIDUZ TARGET_POPCNTD
-#define TARGET_FCTIWUZ TARGET_POPCNTD
+#define TARGET_LFIWZX TARGET_POWER7
+#define TARGET_FCFIDS TARGET_POWER7
+#define TARGET_FCFIDU TARGET_POWER7
+#define TARGET_FCFIDUS TARGET_POWER7
+#define TARGET_FCTIDUZ TARGET_POWER7
+#define TARGET_FCTIWUZ TARGET_POWER7
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
#define TARGET_CTZ TARGET_MODULO
@@ -529,7 +529,7 @@ extern int rs6000_vector_align[];
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
|| TARGET_POWER6 /* ISA 2.05 */ \
- || TARGET_POPCNTD /* ISA 2.06 */ \
+ || TARGET_POWER7 /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
|| TARGET_HARD_FLOAT)
@@ -1738,7 +1738,7 @@ typedef struct rs6000_args
zero. The hardware instructions added in Power9 and the sequences using
popcount return 32 or 64. */
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
- (TARGET_CTZ || TARGET_POPCNTD
\
+ (TARGET_CTZ || TARGET_POWER7 \
? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
: ((VALUE) = -1, 2))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index fd58c332f010..fd2d4d3b7127 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -387,7 +387,7 @@
(const_int 1)
(and (eq_attr "isa" "p7")
- (match_test "TARGET_POPCNTD"))
+ (match_test "TARGET_POWER7"))
(const_int 1)
(and (eq_attr "isa" "p7v")
@@ -2466,7 +2466,7 @@
rtx tmp2 = gen_reg_rtx (<MODE>mode);
rtx tmp3 = gen_reg_rtx (<MODE>mode);
- if (TARGET_POPCNTD)
+ if (TARGET_POWER7)
{
emit_insn (gen_add<mode>3 (tmp1, operands[1], constm1_rtx));
emit_insn (gen_one_cmpl<mode>2 (tmp2, operands[1]));
@@ -2510,7 +2510,7 @@
(define_expand "popcount<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POWER5 || TARGET_POPCNTD"
+ "TARGET_POWER5 || TARGET_POWER7"
{
rs6000_emit_popcount (operands[0], operands[1]);
DONE;
@@ -2527,7 +2527,7 @@
(define_insn "popcntd<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"popcnt<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -6784,7 +6784,7 @@
/* For those old archs in which SImode can't be hold in float registers,
call lrint<mode>si_di to put the result in DImode then convert it via
stack. */
- if (!TARGET_POPCNTD)
+ if (!TARGET_POWER7)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_lrint<mode>si_di (tmp, operands[1]));
@@ -6799,7 +6799,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=d")
(unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && TARGET_POPCNTD"
+ "TARGET_HARD_FLOAT && TARGET_POWER7"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6807,7 +6807,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && !TARGET_POPCNTD"
+ "TARGET_HARD_FLOAT && !TARGET_POWER7"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -10168,7 +10168,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -14435,7 +14435,7 @@
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"bpermd %0,%1,%2"
[(set_attr "type" "popcnt")])
@@ -14813,7 +14813,7 @@
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")]
UNSPEC_ADDG6S))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"addg6s %0,%1,%2"
[(set_attr "type" "integer")])
@@ -14821,7 +14821,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CDTBCD))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"cdtbcd %0,%1"
[(set_attr "type" "integer")])
@@ -14829,7 +14829,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CBCDTD))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"cbcdtd %0,%1"
[(set_attr "type" "integer")])
@@ -14844,7 +14844,7 @@
(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
(match_operand:GPR 2 "register_operand" "r")]
UNSPEC_DIV_EXTEND))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"div<wd><div_extend> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 5e040d84526e..b82dac0237c0 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -188,9 +188,11 @@ mhard-float
Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
Use hardware floating point.
+;; Originally, we used -mpopcntd to indicate ISA 2.6. Keep the switch name,
+;; but change the target macro.
mpopcntd
-Target Mask(POPCNTD) Var(rs6000_isa_flags)
-Use PowerPC V2.06 popcntd instruction.
+Target Mask(POWER7) Var(rs6000_isa_flags)
+Use ISA 2.6 (Power7) instructions.
mfriz
Target Var(TARGET_FRIZ) Init(-1) Save
